Martin L Dorr

US Patent:

6996651, Feb 7, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/207609

Inventors:

Ned D. Garinger - Tempe AZ, US
Martin L. Dorr - Chandler AZ, US
Mark W. Naumann - Tempe AZ, US
Gary A. Walker - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/00

US Classification:

710305, 710316, 370364, 370389

Abstract:

A network with memory device address decoding that enables communication among integrated processing elements, including a network, a processing element and a bus gasket. The network transfers packets between multiple ports, where each port conforms to a consistent port interface protocol. The processing element includes a bus and a memory device programmed with the address of each port, so that a transaction on the bus indicating another port is decoded by the memory device. The bus gasket includes a bus interface that generates packets and a port interface that sends and receives the packets according to the consistent port interface protocol and that uses the decoded address as a destination port address. The memory device may be implemented in any desired manner, such as a memory management unit (MMU) or a direct memory access (DMA) device.

US Patent:

7051150, May 23, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/207600

Inventors:

Mark W. Naumann - Tempe AZ, US
Gary A. Walker - Phoenix AZ, US
Ned D. Garinger - Tempe AZ, US
Martin L. Dorr - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/00

US Classification:

710317, 710 38, 710307, 710316

Abstract:

A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet includes one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency.

US Patent:

7139860, Nov 21, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/207588

Inventors:

Gary A. Walker - Phoenix AZ, US
Ned D. Garinger - Tempe AZ, US
Martin L. Dorr - Chandler AZ, US
Mark W. Naumann - Tempe AZ, US

Assignee:

Freescale Semiconductor Inc. - Austin TX

International Classification:

G06F 13/36
G06F 5/00

US Classification:

710306, 710 45, 710311

Abstract:

An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket includes a processor element interface and a port interface. Each processor element interface of at least two bus gaskets operates according to a first logical layer protocol. Each port interface operates according to a consistent port interface protocol by sending transaction requests and receiving acknowledgements and by sending and receiving packet datums via the corresponding port. The physical layer interface transfers packets between the ports and includes an arbiter and an interconnect coupled to each port. Additional bus gaskets may be added that operate according to a second logical layer protocol which may or may not be compatible with the first. Any bus gasket may be added that is configured to communicate using multiple logical layer protocols.

US Patent:

7200137, Apr 3, 2007

Filed:

Jul 29, 2002

Appl. No.:

10/207459

Inventors:

Martin L. Dorr - Chandler AZ, US
Mark W. Naumann - Tempe AZ, US
Gary A. Walker - Phoenix AZ, US
Ned D. Garinger - Tempe AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H04L 12/28

US Classification:

370351, 370396

Abstract:

A network that maximizes interconnect utilization between integrated processing elements, including ports, an interconnect, port interfaces, and an arbiter. Each port includes arbitration and data interfaces. The interconnect includes selectable data paths between the ports for packet datum transfer. Each port interface includes processing, source and destination interfaces. The source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. The destination interface receives packet datums via a number of available input buffers. Each transaction request includes a transaction size, a packet priority, and a destination port address. The arbiter includes a request queue and a buffer counter for each port and a datum counter for each acknowledged transaction. The arbiter arbitrates among transaction requests based on a selected arbitration scheme, destination buffer availability, data path availability, and priority, and uses the packet datum counters, arbitration latency and data path latency to minimize dead cycles in the interconnect.

US Patent:

7277449, Oct 2, 2007

Filed:

Jul 29, 2002

Appl. No.:

10/207298

Inventors:

Ned D. Garinger - Tempe AZ, US
Martin L. Dorr - Chandler AZ, US
Mark W. Naumann - Tempe AZ, US
Gary A. Walker - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H04L 12/28

US Classification:

370419, 370362

Abstract:

An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address. The arbiter receives transaction requests, arbitrates among transaction requests, provides acknowledgements and controls the interconnect to select data paths between sources and destinations.

US Patent:

58897631, Mar 30, 1999

Filed:

Jun 4, 1996

Appl. No.:

8/658046

Inventors:

Timothy Glenn Boland - Phoenix AZ
Martin Ludwig Dorr - Chandler AZ
Alan Gary Ellis - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 1256

US Classification:

370235

Abstract:

A transfer rate controller (10) allows the originator of the data to determine when the data is transferred on the communications link. A method of regulating the transfer of ATM cells to maintain rate precision and provide flexibility for dynamically adjusting the rates at which cells are transferred has been described. In accordance with information on the chronology of prior transfers, cell loss priority, set of rate parameters, traffic types, and priorities, a scheduler (12) determines and schedules the relative ordering or placement of virtual connections with respect to one another. The finder (14) selects virtual connections for data transfer. Therefore, the transfer rate controller (10) provides individual transfer rates to virtual connections in accordance with the type of data traffic transferred.