Martin A Garrison from 3812 Masters Ct, San Jose, CA 95111, age 70, Phone: 4083651560

Us Patents

Network-Based Integrated Device Identification And Ordering System
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US Patent:

6877033, Apr 5, 2005
Filed:

Nov 6, 2000
Appl. No.:

09/707325
Inventors:

Wanda Carol Garrett - Morgan Hill CA, US
Martin Garrison - San Jose CA, US
Jeffrey Robert Perry - Cupertino CA, US
Richard Joel Levin - Sunnyvale CA, US
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

G06F015/16
US Classification:

709218, 709223, 716 15
Abstract:

Techniques are provided for designing a circuit that satisfies user-specified functional requirements without the user having to obtain additional education or possess specialized software. According to one embodiment, user-specified functional requirements are received over a network from a client executing a browser. The network may be, for example, the Internet. Based on the user-specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. One or more web pages that identify the components are then delivered to the browser over the network. According to one aspect of the invention, the component and topology information is used to generate a schematic diagram that is delivered in a web page to the user over the network.

Method To Perform Thermal Simulation Of An Electronic Circuit On A Network
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US Patent:

6931369, Aug 16, 2005
Filed:

May 1, 2001
Appl. No.:

09/846681
Inventors:

Jeffrey Robert Perry - Cupertino CA, US
Martin Garrison - San Jose CA, US
Richard Levin - Sunnyvale CA, US
Phil Gibson - Sunnyvale CA, US
Vandana A. Sojrani - San Jose CA, US
Khang Nguyen - San Jose CA, US
Wanda Carol Garrett - Morgan Hill CA, US
John D. Perzow - Fort Collins CO, US
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

G06F017/50
US Classification:

703 18, 703 13, 703 14, 703 6, 716 4, 716 5
Abstract:

A method and apparatus for thermally simulating a circuit over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. One or more web pages that identify the components are then delivered to the browser over the network. The component and topology information may be used to generate a schematic diagram that is delivered in a web page to the user over the network. The user may thermally simulate the designed circuit. Many characteristics of the board may be adjusted to provide an accurate thermal simulation.

Method For Creating, Modifying, And Simulating Electrical Circuits Over The Internet
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US Patent:

7441219, Oct 21, 2008
Filed:

Jun 24, 2003
Appl. No.:

10/603493
Inventors:

Jeffrey Robert Perry - Cupertino CA, US
Martin Garrison - San Jose CA, US
Khang Nguyen - San Jose CA, US
Richard Levin - Sunnyvale CA, US
Wanda Carol Garrett - Morgan Hill CA, US
Phillip Gibson - Sunnyvale CA, US
Benjamin H. Lee - Saratoga CA, US
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

G06F 17/50
US Classification:

716 11, 716 4, 703 16
Abstract:

The present invention enables a user to create, modify, simulate and save an electrical circuit using an Internet browser over an Internet connection. The user can change the connectivity of the circuit as well as add and/or remove components in a free form manner. The schematic is displayed within a web page on the user's machine with which the user may interact. Block symbols may be used to represent at least a portion of the schematic.

Visualization Of Tradeoffs Between Circuit Designs
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US Patent:

20100325599, Dec 23, 2010
Filed:

Aug 26, 2010
Appl. No.:

12/869201
Inventors:

Jeffrey R. Perry - Cupertino CA, US
Khanh Nhat Vo - Milpitas CA, US
Dien Mac - San Jose CA, US
Martin Garrison - San Jose CA, US
Phil Gibson - Sunnyvale CA, US
International Classification:

G06F 17/50
US Classification:

716122
Abstract:

A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design requirements indicative of desired power supply designs; query the database for components that satisfy the design requirements; determine a plurality of power supply designs in accordance with the components and the design parameters; determine key parameters of at least a subset of the determined power supply designs; and rank the power supply designs.

Power Supply Architecture System Designer
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US Patent:

20110320175, Dec 29, 2011
Filed:

Jun 27, 2011
Appl. No.:

13/169464
Inventors:

Jeffrey Robert Perry - Cupertino CA, US
Martin Garrison - San Jose CA, US
Dien Mac - San Jose CA, US
Khang Nguyen - Bellevue WA, US
Ajay Padgaonkar - San Jose CA, US
Phil Gibson - , US
Scott Hung - Los Altos CA, US
Werner Berns - Grasbrunn, DE
International Classification:

G06F 17/50
US Classification:

703 1
Abstract:

A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to: receive design parameters indicative of a plurality of power supply loads to be powered; determine a plurality of power supply architectures that may be used to provide power supply solutions satisfying the plurality of loads, each power supply architecture including at least one position requiring a component configured to satisfy a load requirement; for each one of at least a subset of the plurality of power supply architectures, determine, based on the characteristics of the plurality of components, at least one component configured to satisfy the corresponding load requirement for each position of the one of the power supply architectures; and generate at least one power supply design in accordance with the power supply architectures and the determined components.

Field-Programmable Gate Array Power Supply System Designer
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US Patent:

20110320848, Dec 29, 2011
Filed:

Jun 27, 2011
Appl. No.:

13/169419
Inventors:

Jeffrey R. Perry - Cupertino CA, US
Martin Garrison - San Jose CA, US
Dien Mac - San Jose CA, US
Howard Chen - Santa Clara CA, US
Phil Gibson - , US
Thomas Jewell - , US
International Classification:

G06F 1/28
US Classification:

713340
Abstract:

A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design parameters indicative of a plurality of loads of a multiple-load device; determine a plurality of power supply architectures that may be used to provide power supply solutions satisfying the plurality of loads, each power supply architecture including at least one position requiring a component configured to satisfy a load requirement; for each one of at least a subset of the plurality of power supply architectures, determine, based on the characteristics of the plurality of components, at least one component configured to satisfy the corresponding load requirement for each position of the one of the power supply architectures; and generate at least one power supply design in accordance with the power supply architectures and the determined components.

Creating A Pc Board (Pcb) Layout For A Circuit In Which The Components Of The Circuit Are Placed In The Determined Pcb Landing Areas
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US Patent:

6678877, Jan 13, 2004
Filed:

Aug 15, 2001
Appl. No.:

09/930883
Inventors:

Jeffrey Robert Perry - Cupertino CA
Martin Garrison - San Jose CA
Richard Levin - Sunnyvale CA
Phil Gibson - Sunnyvale CA
Vandana A. Sojrani - San Jose CA
Khang Nguyen - San Jose CA
Wanda Carol Garrett - Morgan Hill CA
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

G06F 1750
US Classification:

716 15, 716 16, 716 8, 326101, 361720, 361764
Abstract:

A method and apparatus for PCB layout of a circuit simulated over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. The components are placed on a PC board having landing areas designed to accommodate all of the anticipated component sizes for the type of circuit being designed. The PC board may be cropped to the desired size. The PCB may be cropped automatically or manually by the user.