Martin B Roberts

US Patent:

6475850, Nov 5, 2002

Filed:

Jun 4, 2001

Appl. No.:

09/873808

Inventors:

Michael Violette - Boise ID
Martin Ceredig Roberts - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218238

US Classification:

438203, 438202

Abstract:

A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO /Si N differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.

US Patent:

6486018, Nov 26, 2002

Filed:

Feb 22, 2001

Appl. No.:

09/791229

Inventors:

Martin Ceredig Roberts - Boise ID
Kunal R. Parekh - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438239, 438253, 438256, 438396, 438399

Abstract:

Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material.

US Patent:

6531352, Mar 11, 2003

Filed:

Aug 31, 2000

Appl. No.:

09/653151

Inventors:

Gurtej S. Sandhu - Boise ID
Trung Tri Doan - Boise ID
Howard E. Rhodes - Boise ID
Sujit Sharan - Boise ID
Philip J. Ireland - Nampa ID
Martin Ceredig Roberts - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218238

US Classification:

438200, 438674

Abstract:

The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl and plasma conditions to cause Ti from the TiCl to combine with silicon of the substrate to form TiSi. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800Â C. The silicide is also exposed to the temperatures of at least about 800Â C.

US Patent:

6596632, Jul 22, 2003

Filed:

Mar 13, 2001

Appl. No.:

09/805546

Inventors:

Martin C. Roberts - Boise ID
Sanh D. Tang - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2144

US Classification:

438657, 438659, 438664, 438672

Abstract:

A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

US Patent:

6645806, Nov 11, 2003

Filed:

Aug 28, 2001

Appl. No.:

09/941375

Inventors:

Martin Ceredig Roberts - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438241, 438301, 438302, 438305

Abstract:

The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain regions. A halo region is associated with one of the source/drain regions of the access transistor construction and no comparable halo region is associated with the other of the source/drain regions of the access transistor construction. The invention also encompasses methods of forming DRAM devices.

US Patent:

6673670, Jan 6, 2004

Filed:

Aug 31, 2000

Appl. No.:

09/653152

Inventors:

Martin Ceredig Roberts - Boise ID
Christophe Pierrat - Hsin-Chu, TW

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438253, 438396, 438399

Abstract:

Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location.

US Patent:

6717201, Apr 6, 2004

Filed:

Nov 23, 1998

Appl. No.:

09/198034

Inventors:

Martin Ceredig Roberts - Boise ID
Christophe Pierrat - Hsin-Chu, TW

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 27108

US Classification:

257306, 257307

Abstract:

Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location.

US Patent:

6727139, Apr 27, 2004

Filed:

Oct 17, 2002

Appl. No.:

10/273881

Inventors:

Martin Ceredig Roberts - Boise ID
Kunal R. Parekh - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438239, 438253, 438256, 438396, 438399

Abstract:

Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material.