Martin L Voogel

US Patent:

6768335, Jul 27, 2004

Filed:

Jan 30, 2003

Appl. No.:

10/354520

Inventors:

Steven P. Young - Boulder CO
Michael J. Hart - Palo Alto CA
Venu M. Kondapalli - Sunnyvale CA
Martin L. Voogel - Los Altos CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 738

US Classification:

326 37, 326113, 327407, 327408

Abstract:

A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.

US Patent:

6768338, Jul 27, 2004

Filed:

Jan 30, 2003

Appl. No.:

10/354587

Inventors:

Steven P. Young - Boulder CO
Venu M. Kondapalli - Sunnyvale CA
Martin L. Voogel - Los Altos CA

Assignee:

Xilinx, Inc. - San jose CA

International Classification:

G06F 738

US Classification:

326 44, 326 39, 326113, 327407, 327408

Abstract:

A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.

US Patent:

6949951, Sep 27, 2005

Filed:

Jun 15, 2004

Appl. No.:

10/869777

Inventors:

Steven P. Young - Boulder CO, US
Michael J. Hart - Palo Alto CA, US
Venu M. Kondapalli - Suunyvale CA, US
Martin L. Voogel - Los Altos CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F007/38

US Classification:

326 37, 326 38, 326 39, 326113, 327407, 327408

Abstract:

A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.

US Patent:

7053654, May 30, 2006

Filed:

Jun 15, 2004

Appl. No.:

10/869139

Inventors:

Steven P. Young - Boulder CO, US
Venu M. Kondapalli - Sunnyvale CA, US
Martin L. Voogel - Los Altos CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

326 44, 326 39, 326113, 327407, 327408

Abstract:

A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.

US Patent:

20230055458, Feb 23, 2023

Filed:

Aug 18, 2021

Appl. No.:

17/405073

Inventors:

- San Jose CA, US
Betty LAU - Fremont CA, US
Yanran CHEN - San Jose CA, US
Jun LIU - San Jose CA, US
Martin L. VOOGEL - Niwot CO, US

International Classification:

H03K 19/003
H03K 3/0233
H03K 19/20
G06F 30/392

Abstract:

One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

US Patent:

20210143127, May 13, 2021

Filed:

Nov 8, 2019

Appl. No.:

16/679063

Inventors:

- San Jose CA, US
Steven P. YOUNG - Boulder CO, US
Martin L. VOOGEL - Niwot CO, US
Brian C. GAIDE - Erie CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 25/065
H01L 25/00

Abstract:

An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.