Mary Y Chen

US Patent:

7259444, Aug 21, 2007

Filed:

Jul 20, 2004

Appl. No.:

10/895517

Inventors:

Mary Y. Chen - Oak Park CA, US
Donald A. Hitko - Malibu CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 31/075
H01L 31/105
H01L 31/117
H01L 31/119

US Classification:

257656, 257 10, 257227, 257292, 257458

Abstract:

In one embodiment, an optoelectronic device is provided having a pin photo diode including a semi-insulating substrate or layer, with a patterned implant region of a first dopant type. The pin photo diode includes an upper layer having semiconductor material with a second dopant type. An intermediate layer is provided having a substantially intrinsic semiconductor material. An upper layer contact is provided having a portion with a generally circular interior facing edge. The implant region has a first portion having an outer periphery substantially nonoverlapping with the interior facing edge of the upper layer contact. The implant region includes a contact portion located beyond the upper layer contact. A connecting portion couples the first portion and the contact portion of the implant region. In one embodiment, the device includes a heterojunction bipolar transistor coupled to the pin photo diode.

US Patent:

7470619, Dec 30, 2008

Filed:

Dec 1, 2006

Appl. No.:

11/607494

Inventors:

Mary Y. Chen - Oak Park CA, US
James Chingwei Li - Simi Valley CA, US
Philip H. Lawyer - Thousand Oaks CA, US
Marko Sokolich - Los Angeles CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 21/44
H01L 21/4763

US Classification:

438675, 438618, 438631, 438652, 438674, 438678, 257E23141, 257E21175, 257E21586

Abstract:

Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coating (BARC) on the MML; forming a photoresist layer (PR) on the BARC; removing a portion of the PR; etching the BARC and the MML to expose the SL; plating the exposed SL to form a first plated plug; removing the layers to expose the SL; removing an unplated portion of the SL; depositing an inter layer dielectric (ILD) on the interconnect; etching back the ILD to expose the first plated plug; and depositing a second contact on the first plated plug. Using the procedures described above, a second plated plug is then formed on the first plated plug to form the stackable plugged via interconnect.

US Patent:

7531851, May 12, 2009

Filed:

Feb 28, 2007

Appl. No.:

11/713070

Inventors:

Rajesh D. Rajavel - Oak Park CA, US
Mary Y. Chen - Oak Park CA, US
Steven S. Bui - Simi Valley CA, US
David H. Chow - Newbury Park CA, US
James Chingwei Li - Simi Valley CA, US
Mehran Mokhtari - Thousand Oaks CA, US
Marko Sokolich - Los Angeles CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 31/0328

US Classification:

257197, 257592, 257E27053, 438312, 438341, 438357

Abstract:

An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.

US Patent:

7576409, Aug 18, 2009

Filed:

Aug 10, 2005

Appl. No.:

11/202001

Inventors:

Mary Chen - Oak Park CA, US
Marko Sokolich - Los Angeles CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 31/0328

US Classification:

257560, 257197, 257566, 257563, 257564

Abstract:

A wafer comprising at least one high FHBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.

US Patent:

7582536, Sep 1, 2009

Filed:

Aug 14, 2008

Appl. No.:

12/191482

Inventors:

Rajesh D. Rajavel - Oak Park CA, US
Mary Y. Chen - Oak Park CA, US
Steven S. Bui - Simi Valley CA, US
David H. Chow - Newbury Park CA, US
James Chingwei Li - Simi Valley CA, US
Mehran Mokhtari - Thousand Oaks CA, US
Marko Sokolich - Los Angeles CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 21/331
H01L 21/8222

US Classification:

438312, 438341, 438357, 438906, 257197, 257592, 257E27053, 257E21108, 257E21226

Abstract:

An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.

US Patent:

7655529, Feb 2, 2010

Filed:

Feb 7, 2005

Appl. No.:

11/052935

Inventors:

Mary Chen - Oak Park CA, US
Marko Sokolich - Los Angeles CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 21/331

US Classification:

438312, 257E21387

Abstract:

A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT.

US Patent:

7892881, Feb 22, 2011

Filed:

Feb 23, 2009

Appl. No.:

12/390593

Inventors:

Mary Y. Chen - Oak Park CA, US
Peter W. Deelman - Calabasas CA, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

H01L 21/00

US Classification:

438105, 257 77, 257E21005

Abstract:

In one aspect, a method includes forming a silicon dioxide layer on a surface of a diamond layer disposed on a gallium nitride (GaN)-type layer. The method also includes etching the silicon dioxide layer to form a pattern. The method further includes etching portions of the diamond exposed by the pattern.

US Patent:

8216910, Jul 10, 2012

Filed:

Jun 4, 2009

Appl. No.:

12/478628

Inventors:

Mary Chen - Oak Park CA, US
Marko Sokolich - Los Angeles CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 21/331
H01L 21/8222

US Classification:

438312, 438235, 438309, 438342, 438343, 438350

Abstract:

A wafer comprising at least one high FHBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.