Masaaki Higashitani

US Patent:

6346737, Feb 12, 2002

Filed:

Jul 2, 1998

Appl. No.:

09/109755

Inventors:

Masaaki Higashitani - Sunnyvale CA
Hao Fang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 2900

US Classification:

257511, 257315, 257316, 257500, 257510, 257647

Abstract:

A process which includes forming trench structures ( ) in a substrate ( ) as part of both the STI isolation structure and the LOCOS/STI isolation structure. Thereafter, a field oxide ( ) is formed which simultaneously forms a portion of the STI isolation structure and a portion of the LOCOS/STI isolation structure. Consequently, three different isolation structures may be formed without requiring a substantial increase in the complexity or number of processing steps.

US Patent:

6365945, Apr 2, 2002

Filed:

May 2, 2000

Appl. No.:

09/563024

Inventors:

Michael K. Templeton - Atherton CA
Masaaki Higashitani - Sunnyvale CA
John Jianshi Wang - San Jose CA

Assignee:

Advance Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257395, 257394, 257396, 257397, 257398, 257399, 257400, 257224, 257243

Abstract:

A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insulating regions. The method for fabricating the device includes depositing a nitride over a substrate and selectively covering the active regions with a mask, wherein the mask extends beyond boundaries of the active regions to narrow the width of the insulating regions. Thereafter, a channel stop implant is performed to form channel stops. The mask is then trimmed to the boundaries of the active regions after formation of the channel stops, followed by etching the nitride in exposed areas of the mask. Field oxide is then grown in the insulating regions, whereby the field oxide is self-aligned to the channel stops.

US Patent:

6429479, Aug 6, 2002

Filed:

Mar 9, 2000

Appl. No.:

09/522247

Inventors:

K. Michael Han - San Jose CA
Hao Fang - Cupertino CA
Masaaki Higashitani - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 29788

US Classification:

257315, 438201, 438211, 438257

Abstract:

A single tunnel gate oxidation process for fabricating NAND memory strings where the gate oxide of the select transistors and the floating gate memory transistors are fabricated in a single oxidation step is disclosed. The select gate transistors and the floating gate memory transistors have an oxide thickness of 85 -105. For single tunnel gate approach, a careful selection of the medium doped source/drain region implant conditions is necessary for proper function of the NAND memory string. In one embodiment, the medium doped source/drain region is doped with Arsenic to a concentrations of 10 -10 /cm.

US Patent:

6448593, Sep 10, 2002

Filed:

Jan 26, 2000

Appl. No.:

09/491532

Inventors:

Masaaki Higashitani - Sunnyvale CA
Hao Fang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Ltd.

International Classification:

H01L 2902

US Classification:

257288, 257316, 257355, 257356, 257360, 257408, 438201, 438211, 438230, 438232

Abstract:

The present invention provides a method and apparatus for providing a polysilicon type-1 ESD transistor in a flash memory chip. The method and apparatus include providing a select gate transistor that includes a gate, a floating gate, a medium doped junction, and a source and drain. The method and apparatus further include forming the source and drain by performing a lightly doped drain (LDD) mask and etch, performing a LDD spacer deposition and LDD spacer etch, and performing a N+ implant mask and a N+ implant.

US Patent:

6448609, Sep 10, 2002

Filed:

Oct 28, 1999

Appl. No.:

09/429244

Inventors:

Masaaki Higashitani - Sunnyvale CA
Hao Fang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited

International Classification:

H01L 29792

US Classification:

257326, 257315, 438257, 438241, 438258

Abstract:

A system and method detecting the presence of polysilicon stringers on a memory array using a polysilicon stringer monitor. The polysilicon stringer monitor includes a continuous type-2 layer of polysilicon forming a first row and a second row across the active region and covering the active region in-between the first and second rows. The polysilicon stringer monitor further includes a continuous type-1 layer of polysilicon extending under the first row, wherein the type-1 layer also covers the active area in-between the first and second rows as well as covers the active area under the second row.

US Patent:

6583479, Jun 24, 2003

Filed:

Oct 16, 2000

Appl. No.:

09/688936

Inventors:

Richard M. Fastow - Cupertino CA
Shane C. Hollmer - San Jose CA
Michael Van Buskirk - Saratoga CA
Masaaki Higashitani - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 31062

US Classification:

257390

Abstract:

An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a trench formed in the substrate. The channel length is dependent upon the depth of the trench and therefore a dense array of NROM transistors can be formed without adversely affecting the channel length and therefore the operational performance of the transistor.

US Patent:

6602776, Aug 5, 2003

Filed:

May 23, 2002

Appl. No.:

10/155500

Inventors:

Masaaki Higashitani - Sunnyvale CA
Hao Fang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438612, 438620, 438266, 438598, 438257, 438261

Abstract:

A system and method detecting the presence of polysilicon stringers on a memory array using a polysilicon stringer monitor. The polysilicon stringer monitor includes a continuous type-2 layer of polysilicon forming a first row and a second row across the active region and covering the active region in-between the first and second rows. The polysilicon stringer monitor further includes a continuous type-1 layer of polysilicon extending under the first row, wherein the type-1 layer also covers the active area in-between the first and second rows as well as covers the active area under the second row.

US Patent:

6750103, Jun 15, 2004

Filed:

Feb 27, 2002

Appl. No.:

10/086112

Inventors:

Masaaki Higashitani - Sunnyvale CA
Mark Randolph - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 218247

US Classification:

438261, 438954

Abstract:

A method of fabricating nitride read-only memory (NROM) cells and arrays. The memory device is formed on a substrate. Each memory cell comprises a pair of bit lines extending in a first direction across the substrate, a pair of bit line dielectrics overlaying and covering the pair of bit lines, a charge-trapping layer formed over the channel region between the pair of bit lines, and a conductive connecting block formed on the charge-trapping layer. The charge-trapping layer comprising two oxide-nitride-oxide (ONO) structures separated by a gate oxide layer, where each ONO structures comprises a layer of nitride sandwiched between a bottom oxide layer and a top oxide layer. A plurality of straight, parallel-edged word lines extend across the substrate in a second direction and cross over the bit lines and channel regions. Each word line comprises a conductive material and is separated from the substrate by the conductive connecting blocks and bit lines dielectrics.