Masakazu M Shoji

US Patent:

6366074, Apr 2, 2002

Filed:

Mar 24, 2000

Appl. No.:

09/534189

Inventors:

Masakazu Shoji - Warren NJ

Assignee:

Agere Systems Guardian Corp - Miami Lakes FL

International Classification:

G01R 1900

US Classification:

324 7611, 324607, 324330, 324361, 324765, 324512, 324527

Abstract:

A method for creating signal unidirectionality in electronic circuits is disclosed. This invention describes a method for achieving unidirectionality in an electronic circuit with an input side having a signal source and an output side with a load comprising detecting the current passing through the load on the output side, bypassing a portion of the current passing through the load on the output side, and feeding the bypassed portion of the current on the output side to the input side to achieve unidirectionality. Specifically, unidirectionality in an electronic circuit is accomplished by applying feedback such that the impedance looking into the input of the amplifier is increased. These methods are particularly applicable to negative resistance amplifier circuits.

US Patent:

6496056, Dec 17, 2002

Filed:

Mar 8, 1999

Appl. No.:

09/264070

Inventors:

Masakazu Shoji - Warren NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G05F 302

US Classification:

327543, 327538, 327541

Abstract:

An operating parameter of an integrated circuit is made substantially insensitive to process variations by configuring the circuit such that an environmental parameter, e. g. , supply voltage to a portion of the circuit, is made a function of one or more process parameters, e. g. , conduction threshold voltages and mobilities in that portion of the circuit. In this manner, the effect of the process parameters on the circuit operating parameter may be partially or substantially offset by the effect of the process parameters on the environmental parameter. In an illustrative embodiment, the circuit operating parameter is an oscillation period of a ring oscillator. A voltage regulator generates a reference voltage which is determined at least in part based on known process parameter variations in the ring oscillator. The ring oscillator utilizes the reference voltage generated by the voltage regulator as its supply voltage, and its oscillation period is thereby made insensitive to the process parameter variations. In addition, back-bias effects may be introduced in the voltage regulator to compensate back-bias effects resulting from particular configurations of the ring oscillator.

US Patent:

49029126, Feb 20, 1990

Filed:

Jun 13, 1989

Appl. No.:

7/366340

Inventors:

Federico Capasso - Westfield NJ
Alfred Y. Cho - Summit NJ
Susanta Sen - Scotch Plains NJ
Masakazu Shoji - Warren NJ
Deborah Sivco - Warren NJ

Assignee:

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H01L 29205
H01L 2988

US Classification:

307322

Abstract:

A semiconductor integrated resonant-tunneling device having multiple negative-resistance regions, and having essentially equal current peaks in such regions, is useful as a highly compact element, e. g. , in apparatus designed for ternary logic operations, frequency multiplication, waveform scrambling, memory operation, parity-bit generation, and coaxial-line driving. The device can be made by layer deposition on a substrate and includes a resonant-tunneling structure between contacts such that side-by-side first and third contacts are on one side, and a second contact is on the opposite side of the resonant-tunneling structure.

US Patent:

44880669, Dec 11, 1984

Filed:

Nov 8, 1982

Appl. No.:

6/439938

Inventors:

Masakazu Shoji - Warren NJ

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H03K 19017
H03K 19096

US Classification:

307452

Abstract:

To improve the speed of transfer of information to the databus in data processing apparatus, the bus is periodically precharged and the coupling to the databus is by way of a special clocked CMOS buffer circuit.

US Patent:

45146470, Apr 30, 1985

Filed:

Aug 1, 1983

Appl. No.:

6/519495

Inventors:

Masakazu Shoji - Warren NJ

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H03K 5135
H03K 514
H03K 512
H03K 386

US Classification:

307269

Abstract:

Each chip of a microprocessor chipset is synchronized by an associated controller which adjusts a control signal for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp which compares the output of an internal clock in each chip with a reference system clock.

US Patent:

46688803, May 26, 1987

Filed:

Mar 26, 1984

Appl. No.:

6/593099

Inventors:

Masakazu Shoji - Warren NJ

Assignee:

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H03K 19096
H03K 19173
G06F 738

US Classification:

307469

Abstract:

Additional data processing capability can be added to a programmed logic array (PLA), having an AND plane and an OR plane connected serially between an input register and an output register, by inserting a multistage domino CMOS logic network between the OR plane and the output register. The OR plane is an array of single-stage domino CMOS logic and is timed so that it precharges simultaneously with the multistage network. Without prolonging the individual phase durations or adding any registers, the added domino logic network can have a propagation delay time corresponding to more than one phase of the PLA, and hence the network can have correspondingly more stages and more added data processing capability.

US Patent:

RE325155, Oct 6, 1987

Filed:

Feb 6, 1986

Appl. No.:

6/827270

Inventors:

Masakazu Shoji - Warren NJ

Assignee:

American Telephone and Telegraph Company AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H03K 19017
H03K 19094

US Classification:

307448

Abstract:

In an IGFET circuit having a long string of more than two transistors connected in series between an output terminal and a power supply terminal where the load capacitance across the output terminal is on the same order of magnitude as the parasitic capacitances at the junctures of the transistors in the string, the switching-delay is not significantly reduced by uniformly increasing the conduction channel widths of the transistors in the string. However, according to the present invention, a substantial reduction in the switching delay of such a circuit may be obtained by scaling the conduction channel widths of the transistors in the string so as to provide a positive gradient in conduction channel widths along the string in the direction from the output terminal to the power supply terminal. It is particularly advantageous to use exponential scaling of the conduction channel widths. The present invention is also applicable to transistor strings which include one or more groups of parallel connected transistors.

US Patent:

57868271, Jul 28, 1998

Filed:

Feb 21, 1995

Appl. No.:

8/391804

Inventors:

Milan F. Jukl - Neshanic Station NJ
Norman Loren Schryer - New Providence NJ
Masakazu Shoji - Warren NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G09G 536

US Classification:

345507

Abstract:

A semiconductor memory device contains graphic information which is viewable both by direct, visual observation of the memory and electrically, e. g. , via a TV screen. The device contains a semiconductor chip having a surface and an array of electrically addressable memory cells therewithin. A photograph is made on the chip for storing graphic information projected onto the chip. The photograph comprises pixels which themselves comprise variable value circuit elements of the cells, or which are optically coupled to cell circuit elements for controlling the values thereof in correspondence with the optical characteristics of the pixels. The circuit elements determine the memory content of the cells in correspondence with the graphic information stored in the photograph.