Matthew D Akers

US Patent:

7657682, Feb 2, 2010

Filed:

Sep 14, 2007

Appl. No.:

11/855706

Inventors:

Annette Pagan - Austin TX, US
Matthew D. Akers - Austin TX, US
Christine E. Moran - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 12/00

US Classification:

710244, 370230, 370412, 711151

Abstract:

A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction. The method further includes performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold. The method further includes if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction meets a condition of a set of at least one condition, wherein a condition of the set of at least one condition includes that the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master.

US Patent:

7747889, Jun 29, 2010

Filed:

Jul 31, 2006

Appl. No.:

11/461048

Inventors:

Craig D. Shaw - Austin TX, US
Matthew D. Akers - Austin TX, US
Robert N. Ehrlich - Leander TX, US
Brett W. Murdock - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 1/00
G06F 1/04
G06F 1/12
H03L 7/00
H04L 7/00
G06F 13/00

US Classification:

713500, 713401, 713503, 327161, 375355, 710110, 710317

Abstract:

A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.

US Patent:

8156273, Apr 10, 2012

Filed:

May 10, 2007

Appl. No.:

11/747087

Inventors:

Christine E. Moran - Austin TX, US
Matthew D. Akers - Austin TX, US
Annette Pagan - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/00
G06F 7/38
G06F 13/368
G06F 12/00
G06F 13/26

US Classification:

710110, 326 38, 710121, 710122, 710123, 710240, 710241, 710242, 710243, 710264, 710265

Abstract:

A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI).

US Patent:

8363766, Jan 29, 2013

Filed:

Jun 6, 2008

Appl. No.:

12/134913

Inventors:

Matthew D. Akers - Austin TX, US
Craig D. Shaw - Austin TX, US
Timothy K. Waldrop - Cedar Park TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H04L 7/00

US Classification:

375354

Abstract:

A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer.

US Patent:

20040027742, Feb 12, 2004

Filed:

Aug 9, 2002

Appl. No.:

10/216336

Inventors:

James Miller - Austin TX, US
Geoffrey Hall - Austin TX, US
Alexander Krasin - Mosoow, RU
Michael Stockinger - Austin TX, US
Matthew Akers - Austin TX, US
Vishnu Kamat - Austin TX, US

International Classification:

H02H009/00

US Classification:

361/052000, 361/111000

Abstract:

An Electrostatic Discharge (ESD) protection circuit () includes a plurality of I/O and power supply pad cells () that comprise external pads () and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices () coupled in parallel between an ESD bus () and a VSS bus () and distributed among the plurality of pad cells. One or more trigger circuits () control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus () which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.

US Patent:

20190044861, Feb 7, 2019

Filed:

Sep 26, 2018

Appl. No.:

16/142322

Inventors:

- Santa Clara CA, US
Kenneth Keels - Austin TX, US
Matthew Akers - Cedar Park TX, US

International Classification:

H04L 12/801
H04L 29/06
H04L 12/721
G06F 15/167
H04L 12/807

Abstract:

Technologies for remote direct memory access (RDMA) congestion control include a requester device and a responder device in communication over an Ethernet network. The requester device sends routable RDMA packets to the responder device over the Ethernet network. The packets may be RDMA over Converged Ethernet version 2 (RoCEv2) packets. The responder device determines whether any of the received packets have been marked by the network with a congestion encountered codepoint. If so, the responder device sends an acknowledgment packet with an express congestion notification bit set in the RDMA base transport header. The requester device updates a congestion window as a function of a number of congested packets acknowledged and a total number of packets acknowledged. Those operations may be performed by a network controller of each of the requester device and the responder device. Other embodiments are described and claimed.