Matthew D Hendricks

US Patent:

58930884, Apr 6, 1999

Filed:

Sep 19, 1996

Appl. No.:

8/716907

Inventors:

Matthew C. Hendricks - Palo Alto CA
Kirk R. Martinez - San Jose CA
Naresh U. Mehta - Santa Clara CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1730

US Classification:

707 3

Abstract:

A system and method for performing complex queries in a database system. The method identifies a single type of entity in the database. A table or set of columns is formed that is used to track which entries meet the various subcriteria in a complex query through entry of binary marker bits. Logical operations may be performed on such marker bits to identify those entities meeting the specified search criteria. Through appropriate search planning, the bits may be "reused" during the query search. The method may be used in combination with, for example, index searches and other optimized searching techniques.

US Patent:

61957720, Feb 27, 2001

Filed:

May 2, 1997

Appl. No.:

8/850790

Inventors:

Bruce F. Mielke - Los Altos Hills CA
Matthew C. Hendricks - Palo Alto CA
Howard Marshall - Portola Valley CA
Richard Swan - Portola Valley CA
Lee R. Althouse - Santa Clara CA
Ken A. Ito - San Jose CA

Assignee:

Altera Corporaiton - San Jose CA

International Classification:

G01R 3128
G01R 3102

US Classification:

714724

Abstract:

An electronic circuit tester (e. g. , for testing integrated circuit wafers or packaged integrated circuits) is provided. The tester is preferably based on a relatively inexpensive computer system such as a personal computer and includes at least one high-precision clock circuit that is programmable with respect to frequency and number of clock pulses. The high-precision clock circuit is connectable to the circuit being tested to permit certain timing-critical tests to be performed, even though a large number of other data channels in the tester are controlled by a relatively low speed clock circuit. The tester also includes analog circuitry that can be programmed to provide various analog signals suitable for performing parametric testing on an electronic device under test.

US Patent:

58986286, Apr 27, 1999

Filed:

Apr 17, 1997

Appl. No.:

8/842903

Inventors:

Bruce Mielke - Los Altos Hills CA
Matthew C. Hendricks - Palo Alto CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 700

US Classification:

365201

Abstract:

A method and apparatus for maximizing the data transmission rate from a source data path to selected channels of a destination data path having a different width from the source data path. In a preferred embodiment, the data transfer circuit includes at least one transfer register that is typically of the same width as the data source. Each bit from the transfer register is input to a plurality of multiplexers, each of which typically selects a single bit and outputs the selected bit to the destination.

US Patent:

52009203, Apr 6, 1993

Filed:

Sep 17, 1991

Appl. No.:

7/759944

Inventors:

Kevin A. Norman - Belmont CA
James D. Sansbury - Portola Valley CA
Alan L. Herrmann - Sunnyvale CA
Matthew C. Hendricks - Los Gatos CA
Behzad Nouban - Mountain View CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 1134
G11C 700
G11C 2900

US Classification:

365185

Abstract:

A method for programming programmable EPROM elements in programmable logic arrays. Multiple programming passes are made through the array, with the programming pulses decreasing in duration on each pass.

US Patent:

61804258, Jan 30, 2001

Filed:

Jul 23, 1998

Appl. No.:

9/121247

Inventors:

Bruce Mielke - Los Altos Hills CA
Matthew C. Hendricks - Palo Alto CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 3126
H01L 2166

US Classification:

438 15

Abstract:

A method and apparatus for maximizing the data transmission rate from a source data path to selected channels of a destination data path having a different width from the source data path. In a preferred embodiment, the data transfer circuit includes at least one transfer register that is typically of the same width as the data source. Each bit from the transfer register is input to a plurality of multiplexers, each of which typically selects a single bit and outputs the selected bit to the destination.

US Patent:

60761792, Jun 13, 2000

Filed:

Jan 29, 1997

Appl. No.:

8/790693

Inventors:

Matthew C. Hendricks - Palo Alto CA
Richard Swan - Portola Valley CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 3128
G06F 1100

US Classification:

714742

Abstract:

The present invention provides a method and apparatus for increasing the vector rate of an integrated circuit test system and simplifying the wiring of the tester to the device under test. The tester incorporates circuitry that allows the CPU to remap assignments of tester channels in the CPU address space during testing.

US Patent:

56083378, Mar 4, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/481744

Inventors:

Matthew C. Hendricks - Palo Alto CA
Ernest Allen - Hillsboro OR

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 3128

US Classification:

324765

Abstract:

A method and apparatus for testing an integrated circuit device. An integrated circuit device undergoes testing in at least two different stages of the manufacturing process. At one stage, the semiconductor wafer containing multiple chip dice is probed by a probe tester that tests each of the dice individually. At another stage, after an individual chip die has been encapsulated in a package, a package tester tests and exercises the functions of the chip.