Matthew Monroe

US Patent:

20220262733, Aug 18, 2022

Filed:

May 6, 2022

Appl. No.:

17/738460

Inventors:

- Boise ID, US
Matthew Monroe - Boise ID, US

International Classification:

H01L 23/538
H01L 23/00
H01L 23/13
H01L 23/31
H01L 21/48
H01L 21/56
H01L 25/00
H01L 25/18

Abstract:

A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.

US Patent:

20200227355, Jul 16, 2020

Filed:

Mar 26, 2020

Appl. No.:

16/830693

Inventors:

- Boise ID, US
Matthew Monroe - Boise ID, US

International Classification:

H01L 23/538
H01L 23/00
H01L 23/13
H01L 23/31
H01L 21/48
H01L 21/56
H01L 25/00
H01L 25/18

Abstract:

A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.

US Patent:

20190311987, Oct 10, 2019

Filed:

Apr 5, 2018

Appl. No.:

15/946139

Inventors:

- Boise ID, US
Matthew Monroe - Boise ID, US

International Classification:

H01L 23/538
H01L 23/00
H01L 23/13
H01L 23/31
H01L 21/48
H01L 21/56
H01L 25/00
H01L 25/18

Abstract:

A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.

US Patent:

20190051631, Feb 14, 2019

Filed:

Oct 16, 2018

Appl. No.:

16/162070

Inventors:

- Boise ID, US
Matthew Monroe - Boise ID, US

International Classification:

H01L 25/065
H01L 23/498
H01L 25/00
H01L 23/367
H01L 23/40

Abstract:

Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. At least a portion of a heat-management structure may be located within the window. At least a portion of an outer periphery of an underlying substrate may laterally overlap with an inner portion of the substrate defining the periphery of the window.

US Patent:

20180005983, Jan 4, 2018

Filed:

Aug 16, 2016

Appl. No.:

15/238382

Inventors:

- Boise ID, US
Matthew Monroe - Boise ID, US

International Classification:

H01L 25/065
H01L 23/498
H01L 23/367
H01L 25/00

Abstract:

Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. Semiconductor devices may be supported on the upper surface of the substrate around a periphery of the array of electrically conductive elements. The semiconductor devices may be electrically connected to at least some of the electrically conductive elements of the array by routing elements extending from the semiconductor devices toward the window.