Kai Chirca - Richardson TX, US Joseph R. M. Zbiciak - Arlington TX, US Matthew D. Pierson - Murphy TX, US
International Classification:
G06F 12/08
US Classification:
711122, 711E12057, 711E12024
Abstract:
A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.
Prefetch Stream Filter With Fifo Allocation And Stream Direction Prediction
Kai Chirca - Richardson TX, US Joseph R.M. Zbiciak - Arlington TX, US Matthew D. Pierson - Murphy TX, US Timothy D. Anderson - Dallas TX, US
International Classification:
G06F 12/08
US Classification:
711136, 711137, 711E12017, 711E12057
Abstract:
A prefetch filter receives a memory read request having an associated address for accessing data that is stored in a line of memory. An address window is determined that has an address range that encompasses an address space that is twice as large as the line of memory. In response to a determination of in which half the address window includes the requested line of memory, a prefetch direction is to a first direction or to an opposite direction. The prefetch filter can include an array of slots for storing a portion of a next predicted access and determine a memory stream in response to a hit on the array by a subsequent memory request. The prefetch filter FIFO counter cycles through the slots of the array before wrapping around to a first slot of the array for storing a next predicted address portion.
Prefetch Address Hit Prediction To Reduce Memory Access Latency
Timothy D. Anderson - Dallas TX, US Joseph R. M. Zbiciak - Arlington TX, US Matthew D. Pierson - Murphy TX, US
International Classification:
G06F 12/08
US Classification:
711137, 711117, 711E12017
Abstract:
A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined in response to a prefetch address stored in a slot of an array for storing portions of predicted addresses and associated with a slot in accordance with an order in which a prefetch FIFO counter is modified to select the slots of the array. Data is prefetched from a lower-level hierarchical memory in accordance with a next predicted address and provisioned the prefetched data to minimize a read time for reading the prefetched data. The provisioned prefetched data is read-out when the address of the memory request is associated with the next predicted address.
Multicore Bus Architecture With Wire Reduction And Physical Congestion Minimization Via Shared Transaction Channels
- Dallas TX, US Timothy Anderson - University Park TX, US Joseph Zbiciak - Farmers Branch TX, US Abhijeet A. Chachad - Plano TX, US Kai Chirca - Dallas TX, US Matthew D. Pierson - Murphy TX, US
International Classification:
G06F 13/42 G06F 13/362
Abstract:
The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.
- Dallas TX, US Timothy David ANDERSON - University Park TX, US Joseph ZBICIAK - San Jose CA, US David E. SMITH - Allen TX, US Matthew David PIERSON - Frisco TX, US
Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.
Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System
- Dallas TX, US Timothy D. Anderson - University Park TX, US Joseph R.M. Zbiciak - San Jose TX, US Abhijeet A. Chachad - Plano TX, US Kai Chirca - Dallas TX, US Matthew D. Pierson - Murphy TX, US
This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
- Dallas TX, US Timothy David ANDERSON - University Park TX, US Joseph ZBICIAK - San Jose CA, US David E. SMITH - Allen TX, US Matthew David PIERSON - Frisco TX, US
Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.
Multi-Power-Domain Bridge With Prefetch And Write Merging
- Dallas TX, US Kai CHIRCA - Dallas TX, US Matthew David PIERSON - Frisco TX, US
International Classification:
G06F 12/0855 G06F 12/10 G06F 13/40 G06F 13/16
Abstract:
Techniques for accessing data, comprising receiving a first memory request associated with a first clock domain, converting a first memory address of the first memory request from a first memory address format associated with the first clock domain to a second memory address format associated with the second clock domain, transitioning the first memory request to a second clock domain, creating a first scoreboard entry associated with the first memory request, transmitting the first memory request to a memory based on the converted first memory address, receiving a first response to the first memory request, transitioning the first response to the second clock domain and clearing the first scoreboard entry based on the received response.
NetBase Solutions, Inc. - Greater New York City Area since 2012
Senior Social Analyst
Porter Novelli Mar 2011 - Mar 2012
Senior Manager, Digital & Social Media Analytics
NM Incite, a Nielsen/McKinsey joint venture Jun 2010 - Mar 2011
Engagement Manager - Telecom, Media & Entertainment, Education, and Government
Nielsen BuzzMetrics Jan 2010 - Jun 2010
Strategic Account Manager - Technology & Telecom
The Nielsen Company Feb 2009 - Dec 2009
Senior Technology & Telecom Analyst
Education:
Pomona College
Clarkstown South
Skills:
Sentiment Analysis Process Optimization Web Mining Web Analytics Consumer Insights Consumer Behavior User Acceptance Testing Campaign Optimization Troubleshooting Blogger Outreach Nielsen Microblogging Microsoft Office Facebook Mobile Entertainment Market Research PowerPoint Social Media Emerging Technologies Software Training Mobile Games Social Media Measurement Microsoft Excel Customer Insight Factiva Brandwatch Web Marketing Issues Managment Radian6 Sysomos Nielsen Data Tracx
Honor & Awards:
- Porter Novelli: PRNews Digital PR Award Winner - Digital Marketing Campaign - $500K+ (HP Inkology) - October 2012
- Nielsen: Placed second in corporate Global Efficiency Challenge contest - December 2010
- Nielsen "Simply Excellent" award, in recognition of
"exceeding client expectations with superior insights and analysis" - 2010
- Nielsen “Simply Excellent” award, in recognition of the successful execution of BuzzMetrics’ first multi-country client engagement - 2009
- Best Consumer Knowledge Gameloft NY - 2007
- Jeopardy!: August 2006 to April 2007 – In contestant pool for TV show’s 23rd season
- ACUI College Bowl: 2004 – Team Captain and 7th highest individual scorer Region 15 tournament (CA, NV, HI), 2002 – Team Captain, top individual scorer Region 15 tournament, 3rd place team finish
- Claremont Colleges Ballroom Dance Company: Member 2004 U.S. National Collegiate Championship team
- American Legion Boys Nation 2000: 1 of 2 representatives from New York and 96 nationally
Certifications:
WOM-COMM Online Certificate Program - Ethics, WOMMA (Word of Mouth Marketing Association)
Teaching Trust
Program Officer
Laveen Elementary School District 2010 - May 2014
Assistant Principal
Laveen Elementary School District Jul 2008 - Jun 2010
Instructional Coach
Teach For America 2009 - 2009
Director of Workshops and Resources
Laveen Elementary School District Jul 2005 - Jun 2008
8Th Grade Language Arts and Literature Teacher
Education:
Northern Arizona University 2011 - 2014
Doctorates, Doctor of Education, Leadership, Education
University of Missouri - Columbia 2001 - 2005
Skills:
Curriculum Design Curriculum Development Educational Technology Tutoring K 12 Teacher Training Staff Development Community Outreach Literacy Program Development Educational Leadership Higher Education Instructional Design K 12 Education Nonprofits Special Education Teaching
Texas Instruments since Jun 2007
Design Engineer
University of California Aug 2005 - May 2007
Graduate Student Researcher
Education:
University of California, Berkeley 2005 - 2007
Masters, Electrical Engineering
The University of Texas at Austin 2001 - 2005
Bachelors, Electrical Engineering
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