Matthew T Reynolds

US Patent:

7951688, May 31, 2011

Filed:

Jul 17, 2008

Appl. No.:

12/174863

Inventors:

Minhua Li - Sandy UT, US
Qi Wang - Sandy UT, US
Gordon Sim - Sandy UT, US
Matthew Reynolds - Sandy UT, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Hamza Yilmaz - Saratoga CA, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/30
H01L 21/46

US Classification:

438458, 438110, 438118, 438459, 438462, 438464, 257E21214, 257E21237, 257E21599

Abstract:

A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

US Patent:

8158506, Apr 17, 2012

Filed:

May 5, 2008

Appl. No.:

12/115254

Inventors:

Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Michael D. Gruenhagen - Sandy UT, US
Matthew R. Reynolds - Sandy UT, US
Romel N. Manatad - Mandaue, PH
Jan Vincent C. Mancelita - Mandaue, PH

Assignee:

Fairchild Semiconductor Corporation - San Jose CA

International Classification:

H01L 21/44

US Classification:

438613, 257739

Abstract:

Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.

US Patent:

8343852, Jan 1, 2013

Filed:

Apr 27, 2011

Appl. No.:

13/095584

Inventors:

Minhua Li - Sandy UT, US
Qi Wang - Sandy UT, US
Gordon Sim - Sandy UT, US
Matthew Reynolds - Sandy UT, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Hamza Yilmaz - Saratoga CA, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/00

US Classification:

438462, 438464, 257E21214, 257E21237, 257E21599

Abstract:

A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

US Patent:

8624393, Jan 7, 2014

Filed:

Feb 24, 2012

Appl. No.:

13/404317

Inventors:

Suku Kim - South Jordan UT, US
James Murphy - South Jordan UT, US
Matthew Reynolds - Sandy UT, US
Romel Manatad - Mandaue, PH
Jan Mancelita - Mandaue, PH
Michael Gruenhagen - Salt Lake City UT, US

Assignee:

Fairchild Semiconductor Corporation - San Jose CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257738, 257739, 257E21508, 257E23069, 438613

Abstract:

Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.