Matthew A Rowley

US Patent:

20220415368, Dec 29, 2022

Filed:

Aug 29, 2022

Appl. No.:

17/897929

Inventors:

- Boise ID, US
Matthew D. Rowley - Boise ID, US

International Classification:

G11C 5/14
G06F 1/3296
G06F 1/28

Abstract:

A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.

US Patent:

20230073948, Mar 9, 2023

Filed:

Nov 16, 2022

Appl. No.:

18/056092

Inventors:

- Boise ID, US
Matthew David Rowley - Boise ID, US

International Classification:

G06F 3/06
G11C 5/14

Abstract:

Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

US Patent:

20230068931, Mar 2, 2023

Filed:

Nov 11, 2022

Appl. No.:

18/054770

Inventors:

- Boise ID, US
Matthew David Rowley - Boise ID, US

International Classification:

G11C 5/14
G06F 1/26
G06F 1/28

Abstract:

A power management circuit receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the circuit generates an interrupt signal causing the memory system to shut down safely without data loss.

US Patent:

20210278893, Sep 9, 2021

Filed:

May 21, 2021

Appl. No.:

17/327282

Inventors:

- Boise ID, US
Matthew D. Rowley - Boise ID, US

International Classification:

G06F 1/3296
G06F 13/20
G06F 13/40
G06F 1/3206
G06F 1/3234
G06F 1/3221

Abstract:

A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.

US Patent:

20210165586, Jun 3, 2021

Filed:

Feb 11, 2021

Appl. No.:

17/174211

Inventors:

- Boise ID, US
Matthew David Rowley - Boise ID, US

International Classification:

G06F 3/06
G06F 1/3246
G06F 1/3225
G06F 11/34

Abstract:

A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.

US Patent:

20210110850, Apr 15, 2021

Filed:

Dec 17, 2020

Appl. No.:

17/124582

Inventors:

- Boise ID, US
Matthew D. Rowley - Boise ID, US

International Classification:

G11C 5/14
G06F 1/30
G06F 1/3234
G06F 1/3296

Abstract:

A method of operating a memory sub-system includes receiving an input voltage at a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR). The method includes determining whether the input voltage corresponds to a low power mode of the memory sub-system and that the input voltage is higher than an uppermost supply voltage at which a memory component of the memory sub-system is configured to operate. The method further includes selectably coupling, responsive to a determination of the low power mode, the CVD and the LVR and sequentially reducing the input voltage by the CVD and the LVR to a supply voltage for the memory component, where the supply voltage is not higher than the uppermost supply voltage at which the memory component is configured to operate.

US Patent:

20210089115, Mar 25, 2021

Filed:

Nov 16, 2020

Appl. No.:

17/099158

Inventors:

- Boise ID, US
Matthew David Rowley - Boise ID, US

International Classification:

G06F 1/3296
G06F 12/02
G11C 16/26
G11C 16/30
H01L 27/11526
G11C 7/20
G11C 7/22
H01L 27/11521
G11C 5/14

Abstract:

Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.

US Patent:

20210034086, Feb 4, 2021

Filed:

Jul 29, 2019

Appl. No.:

16/525393

Inventors:

- Boise ID, US
Matthew D. Rowley - Boise ID, US

International Classification:

G05F 1/575
H02M 3/158

Abstract:

Various embodiments described herein provide a system that uses a capacitor-based power converter to generate a gate voltage (e.g., boot strap voltage) for a buck converter. According to various embodiments described herein, the capacitor-based power converter includes at least one of a combination of a capacitive voltage divider circuit with a low-dropout (LDO) regulator, or a combination of a capacitive doubler circuit with an LDO regulator, to generate the gate voltage for the buck converter.