Matthew D Rowley

US Patent:

7187207, Mar 6, 2007

Filed:

Jun 27, 2005

Appl. No.:

11/168034

Inventors:

Matthew D. Rowley - Austin TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19/0175
H03K 19/094
H03K 19/20
H03K 19/086

US Classification:

326 83, 326 62, 326 63, 326 64, 326 65, 326 66, 326 67, 326 68, 326 80, 326 81, 326 82, 326 84, 326 85, 326 86, 326 87, 326112, 326113, 326114, 326115, 326126, 326127, 327 52, 327 65

Abstract:

The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

US Patent:

7279974, Oct 9, 2007

Filed:

Jun 10, 2005

Appl. No.:

11/150448

Inventors:

Matthew D. Rowley - Austin TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3/45

US Classification:

330253, 330257

Abstract:

The fully differential large swing variable gain amplifier circuit includes: a first 5-transistor transconductor having a common mode node; and a second 5-transistor transconductor having a common mode node coupled to the common mode node of the first 5-transistor transconductor, wherein the second 5-transistor transconductor operates 180 degrees out of phase with the first 5-transistor transconductor.

US Patent:

7986159, Jul 26, 2011

Filed:

Jul 16, 2010

Appl. No.:

12/838226

Inventors:

Jawaid Ahmad - Plano TX, US
Matthew D. Rowley - Parker TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19/003
H03K 19/173
H05K 7/10

US Classification:

326 21, 326 38, 710301

Abstract:

With conventional redrivers used for external Serial Advanced Technology Attachment (eSATA), there is no ability to indicated to a host that an external device (like a hard disk drive) is not present. As a result, power is consumed by a host because of nearly continual transmission of communication reset signals. Here, a redriver has been provided that includes a cable disconnect terminal and circuitry within a controller that is able to detect whether an external device is present. This redriver enables a host to be powered down or placed in a low power mode while also enabling the use an eSATA compliant connector.

US Patent:

8643969, Feb 4, 2014

Filed:

Apr 26, 2012

Appl. No.:

13/457175

Inventors:

Rajarshi Mukhopadhyay - Allen TX, US
Matthew D. Rowley - Parker TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 5/09

US Classification:

360 46

Abstract:

A method is provided. A first CMOS switch is deactivated while activating a second CMOS switch to cause the portion of the write signal to transition from a first direct current (DC) voltage to a first peak voltage. After a first interval, the second CMOS switch is deactivated while activating a third CMOS switch to cause the portion of the write signal to transition from the first peak voltage to a second DC voltage. After a second interval, the third CMOS switch is deactivated while activating a fourth CMOS switch to cause the portion of the write signal to transition from the second DC voltage to a second peak voltage After a third interval, the fourth CMOS switch is deactivated while activating the first CMOS switch to cause the portion of the write signal to transition from the second peak voltage to the first DC voltage.

US Patent:

20050285677, Dec 29, 2005

Filed:

Jan 31, 2005

Appl. No.:

11/047195

Inventors:

Matthew Rowley - Austin TX, US

International Classification:

H03F003/45

US Classification:

330259000

Abstract:

A fully balanced transconductor circuit, such as by utilizing two 5 transistor tranconductors in a single circuit sharing the common mode node and operating them 180 degrees out of phase, to realize a current source in saturation under all conditions. The present invention may be utilized in a low power circuit with good jitter performance and large output swings.

US Patent:

20130257514, Oct 3, 2013

Filed:

Mar 30, 2012

Appl. No.:

13/435578

Inventors:

Matthew D. Rowley - Parker TX, US
Rajarshi Mukhopadhyay - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 17/687

US Classification:

327424

Abstract:

An apparatus is provided. A first switch is coupled between first and third nodes in an H-bridge. A second switch is coupled between first and fourth nodes in the H-bridge. A third switch is coupled between the second and third nodes. A fourth switch is coupled between second and fourth nodes in the H-bridge. A first source-follower is coupled to the first node of the H-bridge and the first supply rail, and the first source-follower is configured to receive a first reference signal. A second source-follower is coupled to the second node of the H-bridge and the second supply rail, and the second source-follower is configured to receive a second reference signal.

US Patent:

6603964, Aug 5, 2003

Filed:

Sep 5, 2000

Appl. No.:

09/655318

Inventors:

Matthew D. Rowley - Weston FL
David E. Bockelman - Weston FL

Assignee:

Motorola, Inc. - Schamburg IL

International Classification:

H04B 128

US Classification:

455333, 455326, 327210

Abstract:

A mixer circuit ( ) includes two balanced transmission gate mixers ( ). The mixer circuit ( ) balances charge injection mechanisms which reduces carrier feedthrough in the preferred embodiment. The inputs signals provided to the second transmission gate mixer ( ) are reversed as compared to those provided to the first transmission gate mixer ( ). By reversing the forward path through the second transmission gate mixer ( ), charge injection parasitics seen by the first transmission gate mixer ( ) are canceled by those in the second transmission gate mixer ( ).

US Patent:

20220415368, Dec 29, 2022

Filed:

Aug 29, 2022

Appl. No.:

17/897929

Inventors:

- Boise ID, US
Matthew D. Rowley - Boise ID, US

International Classification:

G11C 5/14
G06F 1/3296
G06F 1/28

Abstract:

A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.