Matthew A Tyler

US Patent:

7456441, Nov 25, 2008

Filed:

Sep 15, 2006

Appl. No.:

11/532477

Inventors:

Matthew A. Tyler - Kaysville UT, US
John J. Naughton - Idaho Falls ID, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

H01L 29/74

US Classification:

257173, 257355, 361 915

Abstract:

A current dissipation circuit that dissipates excess current to or from a circuit node when that monitored circuit node experiences abnormal voltage conditions, rather than having that excess current being dissipated through other protected circuitry. The current dissipation circuit may use single well technology, and may even provide reverse voltage protection without necessarily triggering more significant current dissipation. In another embodiment, the current dissipation circuit is provided by a series connection of at least five alternating p-type and n-type regions provided between the monitored circuit node and a current source or sink.

US Patent:

7526693, Apr 28, 2009

Filed:

Mar 9, 2006

Appl. No.:

11/371661

Inventors:

David J. Willis - Murray UT, US
Matthew Austin Tyler - Kaysville UT, US
Justin Mark Gedge - Eagle Mountain UT, US
Mark R. Whitaker - Draper UT, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

G01R 31/28

US Classification:

714724, 714 36, 714 48, 714740, 714742, 702 98, 702 85, 3652257, 36518503, 712 39, 712 40, 712 43, 31856817, 318590, 31840009, 31840011, 710 14

Abstract:

A circuit that includes a controller and at least one control I/O pin. When the controller is placed into an initial state, the controller initializes the circuit into an initial operation mode. Depending on whether or not signal(s) satisfying predetermined criteria are applied to at least one of the control I/O pins, the controller will cause the circuit to enter one of two or more post-initial operation modes. Accordingly, by initializing the controller, and by controlling a signal on the control I/O pin(s), the operating mode of the circuit may be controlled. In one embodiment, a given control pin might be configurable to be both analog and digital, depending on the circuit's operation mode.

US Patent:

7776677, Aug 17, 2010

Filed:

Mar 30, 2009

Appl. No.:

12/414071

Inventors:

John J. Naughton - Idaho Falls ID, US
Matthew Tyler - Kaysville UT, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

H01L 21/8238

US Classification:

438201, 438211, 257E21179, 257E21422, 257E2168

Abstract:

In one embodiment, an EEPROM device is formed to include a metal layer having an opening therethrough. The opening overlies a portion of a floating gate of the EEPROM device.

US Patent:

7825454, Nov 2, 2010

Filed:

Jun 3, 2010

Appl. No.:

12/793403

Inventors:

John J. Naughton - Idaho Falls ID, US
Matthew Tyler - Kaysville UT, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

H01L 29/76
H01L 29/788

US Classification:

257314, 257315, 257E29129, 257E293

Abstract:

In one embodiment, an EEPROM device is formed to include a metal layer having an opening therethrough. The opening overlies a portion of a floating gate of the EEPROM device.

US Patent:

7940499, May 10, 2011

Filed:

Sep 15, 2006

Appl. No.:

11/532478

Inventors:

Matthew A. Tyler - Kaysville UT, US
John J. Naughton - Idaho Falls ID, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

H02H 9/00
H02H 3/08
H02H 9/02

US Classification:

361 56, 361 931

Abstract:

Current protection in integrated circuit having multiple pads. Different types of current protection structures may be associated with different pads. A common current discharge or charge path may be used to provide current to or draw current from various of these heterogenic current protection structures. Since a common current discharge or charge path is used, the metallization used to formulate a discharge solution is significant simplified. Additionally, the protection structures may be provided with selectively conductive regions that are approximately radially symmetrical around the circumference of the pad. Accordingly, if the protection structures are slightly off center with respect to the bond pad (due to, for example, mask alignment error), the error in the amount of active region around the circumference of the pad is at least partially averaged out.

US Patent:

8390297, Mar 5, 2013

Filed:

Oct 2, 2009

Appl. No.:

12/572870

Inventors:

Riley D. Beck - Eagle Mountain UT, US
Kent D. Layton - Lehi UT, US
Matthew A. Tyler - Kaysville UT, US
Scott R. Grange - Pleasant Grove UT, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

G01R 31/14

US Classification:

324509

Abstract:

A method and circuit for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter.

US Patent:

20130214800, Aug 22, 2013

Filed:

Jan 29, 2013

Appl. No.:

13/752565

Inventors:

Riley D. Beck - Eagle Mountain UT, US
Kent D. Layton - Lehi UT, US
Matthew A. Tyler - Kaysville UT, US
Scott R. Grange - Pleasant Grove UT, US

International Classification:

G01R 27/16

US Classification:

324691

Abstract:

A method and circuit for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter.

US Patent:

20220231274, Jul 21, 2022

Filed:

Aug 24, 2021

Appl. No.:

17/410696

Inventors:

- Cambridge MA, US
Naoki OTA - Lexington MA, US
Matthew R. TYLER - New York NY, US
Richard K. HOLMAN - Wellesley MA, US
Ricardo BAZZARELLA - Woburn MA, US
Mark DUDZIAK - Sharon MA, US

Assignee:

24M Technologies, Inc. - Cambridge MA

International Classification:

H01M 4/139
H01M 4/04

Abstract:

Embodiments described herein relate generally to systems and methods for continuously and/or semi-continuously manufacturing semi-solid electrodes and batteries incorporating semi-solid electrodes. In some embodiments, the process of manufacturing a semi-solid electrode includes continuously dispensing a semi-solid electrode slurry onto a current collector, separating the semi-solid electrode slurry into discrete portions, and cutting the current collector to form a finished electrode.