Matthias Baenninger

US Patent:

20170236835, Aug 17, 2017

Filed:

Feb 16, 2017

Appl. No.:

15/434544

Inventors:

- Plano TX, US
Jin LIU - Milpitas CA, US
Kazuya TOKUNAGA - Yokkaichi, JP
Matthias BAENNINGER - Palo Alto CA, US
Hiroyuki KINOSHITA - Yokkaichi, JP
Murshed CHOWDHURY - Milpitas CA, US
Jiyin XU - Yokkaichi, JP
Dai IWATA - Yokkaichi, JP
Hiroyuki OGAWA - Yokkaichi, JP
Kazutaka YOSHIZAWA - Yokkaichi, JP
Yasuaki YONEMOCHI - Yokkaichi, JP

International Classification:

H01L 27/11582
H01L 27/11519
H01L 29/788
H01L 29/06
H01L 29/10
H01L 23/528
H01L 27/11526
H01L 29/423
H01L 21/28
H01L 21/311
H01L 21/764
H01L 23/29
H01L 23/31
H01L 27/11521
H01L 27/11565
H01L 27/11568
H01L 27/11573
H01L 27/11556

Abstract:

An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

US Patent:

20160300848, Oct 13, 2016

Filed:

Apr 7, 2015

Appl. No.:

14/680414

Inventors:

- Plano TX, US
Matthias BAENNINGER - Menlo Park CA, US
Stephen SHI - Milpitas CA, US
Johann ALSMEIER - San Jose CA, US

International Classification:

H01L 27/115
H01L 21/28
H01L 23/522
H01L 21/768
H01L 29/788
H01L 23/528

Abstract:

Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device can be reduced by forming composite electrically conductive layers and/or use of a metal oxide material for an insulating spacer for backside contact trenches. Each composite electrically conductive layer includes a doped semiconductor material portion in proximity to memory stack structures and a metallic material portion in proximity to a backside contact trench. Fluorine generated from the metallic material layers can escape readily through the backside contact trench. The semiconductor material portions can reduce mechanical stress. Alternatively or additionally, a dielectric metal oxide employed as an insulating spacer formed on the sidewalls of the backside contact trench, thereby blocking a diffusion path for fluorine radicals generated from the metallic material of the electrically conductive layers, and preventing electrical shorts between electrically conductive layers and/or a backside contact via structure.

US Patent:

20160268209, Sep 15, 2016

Filed:

Mar 10, 2015

Appl. No.:

14/643280

Inventors:

- Plano TX, US
Matthias BAENNINGER - Menlo Park CA, US
Stephen SHI - Milpitas CA, US
Johann ALSMEIER - San Jose CA, US
Henry CHIEN - San Jose CA, US

International Classification:

H01L 23/532
H01L 21/768
H01L 23/522
H01L 27/115
H01L 23/528

Abstract:

A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity. Each electrically conductive layer contains a material from a portion of a respective second epitaxial semiconductor layer.

US Patent:

20160141294, May 19, 2016

Filed:

Oct 29, 2015

Appl. No.:

14/926347

Inventors:

- Plano TX, US
Sateesh Koka - Milpitas CA, US
Raghuveer S. Makala - Campbell CA, US
Rahul Sharangpani - Fremont CA, US
Matthias Baenninger - Menlo Park CA, US
Jayavel Pachamuthu - San Jose CA, US
Johann Alsmeier - San Jose CA, US

International Classification:

H01L 27/115
H01L 29/66
H01L 29/792

Abstract:

A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor material.

US Patent:

20150357413, Dec 10, 2015

Filed:

Jun 5, 2014

Appl. No.:

14/297106

Inventors:

- Plano TX, US
Matthias Baenninger - Palo Alto CA, US
Akira Matsudaira - San Jose CA, US
Yao-Sheng Lee - Tampa FL, US
Johann Alsmeier - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

H01L 29/10
H01L 27/115

Abstract:

A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.