Max Earl Nielsen

US Patent:

20130188457, Jul 25, 2013

Filed:

Jan 24, 2012

Appl. No.:

13/357593

Inventors:

Max E. NIELSEN - Orting WA, US
Ricky D. JORDANGER - Allen TX, US
Ismail H. OGUZMAN - Plano TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H04B 1/06
H04B 1/02

US Classification:

367135, 367137

Abstract:

In at least some embodiments, an ultrasound system includes an ultrasound transducer and a bi-directional transistor coupled to the ultrasound transducer. The ultrasound system also includes an ultrasound receiver coupled to the bi-directional transistor. The bi-directional transistor operates to selectively connect the ultrasound transducer to ground and to selectively connect the ultrasound transducer to the ultrasound receiver.

US Patent:

20140055003, Feb 27, 2014

Filed:

Aug 21, 2012

Appl. No.:

13/590672

Inventors:

Max Earl Nielsen - Orting WA, US
Ricky Dale Jordanger - Allen TX, US
Ismail Hakki Oguzman - Plano TX, US
Zheng Gao - Dallas TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 41/09

US Classification:

310317

Abstract:

A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the samples to modify drive parameters. Use of multiple sample periods enables independent measurement and adjustment of different portions of the transducer driving waveform to ensure mirror symmetry.

US Patent:

20220291709, Sep 15, 2022

Filed:

Mar 11, 2021

Appl. No.:

17/199028

Inventors:

MAX E. NIELSEN - CALDWELL ID, US
PHILLIP HENRY FISCHER - LINTHICUM HEIGHTS MD, US

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

International Classification:

G06F 1/10
H01P 7/08

Abstract:

One example includes a clock distribution system. The system includes a resonator feed network comprising a plurality of resonant transmission lines that each propagate a clock signal. The system also includes at least one resonator spine. Each of the at least one resonator spine can be conductively coupled to at least one of the resonant transmission lines, such that each of the at least one resonator spine propagates the clock signal. The system further includes at least one resonator rib conductively coupled to at least one of the at least one resonator spine. Each of the at least one resonator rib can be arranged as a standing wave resonator to propagate the clock signal.

US Patent:

20220286129, Sep 8, 2022

Filed:

Feb 11, 2022

Appl. No.:

17/669502

Inventors:

- Redmond WA, US
Max Earl NIELSEN - Pocatello ID, US

International Classification:

H03K 17/92
G06F 1/10

Abstract:

Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

US Patent:

20220286136, Sep 8, 2022

Filed:

Mar 8, 2021

Appl. No.:

17/194547

Inventors:

- Redmond WA, US
Max Earl NIELSEN - Pocatello ID, US

International Classification:

H03K 19/195
H01L 39/02
H03K 19/0185
H03K 19/00

Abstract:

Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.