Max Garold Nielsen

US Patent:

20220286129, Sep 8, 2022

Filed:

Feb 11, 2022

Appl. No.:

17/669502

Inventors:

- Redmond WA, US
Max Earl NIELSEN - Pocatello ID, US

International Classification:

H03K 17/92
G06F 1/10

Abstract:

Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

US Patent:

20220286136, Sep 8, 2022

Filed:

Mar 8, 2021

Appl. No.:

17/194547

Inventors:

- Redmond WA, US
Max Earl NIELSEN - Pocatello ID, US

International Classification:

H03K 19/195
H01L 39/02
H03K 19/0185
H03K 19/00

Abstract:

Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.