Mayank X Gupta

Address:

390 Elan Vlg Ln, San Jose, CA 95134

Phone:

4083492136

VIN:

1HGCP3F86BA030979

Make:

HONDA

Model:

ACCORD

Year:

2011

US Patent:

6694408, Feb 17, 2004

Filed:

May 1, 2000

Appl. No.:

09/562062

Inventors:

Javier Villagomez - San Jose CA 95134
Mayank Gupta - Sunnyvale CA 94086
Edward T. Pak - Sunnyvale CA 94086

International Classification:

G06F 1200

US Classification:

711133, 711134, 711128

Abstract:

The invention provides a system and method for executing a replacement selection algorithm embedded in each associativity of a cache memory architecture. Each associativity in a cache has an internal control logic that governs the process for replacing a cache line when a certain condition occurs, such as a presence of a TagHit. A designated set of control signals is used in an associativity control logic for corresponding with an external control logic. An associativity control logic within an associativity provides an internal capability to determine whether a TagHit condition occurs as well as volunteering the associativity for replacement. The preferred replacement algorithm is implemented using an approximation to Not the Most Recently Used Associativity (NMRU).

US Patent:

7487369, Feb 3, 2009

Filed:

May 1, 2000

Appl. No.:

09/562071

Inventors:

Mayank Gupta - Sunnyvale CA, US
Edward T. Pak - Saratoga CA, US
Javier Villagomez - San Jose CA, US
Peter H. Voss - Aromas CA, US

Assignee:

RMI Corporation - Cupertino CA

International Classification:

G06F 1/32
G06F 12/00

US Classification:

713300, 711118

Abstract:

The invention provides a cache architecture that selectively powered-up a portion of data array in a pipelined cache architecture. A tag array is first powered-up, but the data array is not powered-up during this time, to determine whether there is a tag hit from the decoded index address comparing to the tag compare data. If there is a tag hit, during a later time, a data array is then powered-up at that time to enable a cache line which corresponds with the tag hit for placing onto a data bus. The power consumed by the tag represents a fraction of the power consumed by the data array. A significant power is conserved during the time in which the tag array is assessing whether a tag hit occurs while the data array is not powered-on at this point.

US Patent:

7518067, Apr 14, 2009

Filed:

Sep 27, 2006

Appl. No.:

11/528253

Inventors:

Mayank Gupta - Sunnyvale CA, US
Mario Pelella - Mountain View CA, US
Farzin Assad - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01R 4/38
H05K 9/00

US Classification:

174376, 174384, 174387, 257660, 361818

Abstract:

According to one exemplary embodiment, a structure comprises an electronic device situated over a substrate of a semiconductor die. The structure further includes a metal cage comprising a number of contacts situated over the substrate and surrounding the electronic device. The contacts form a lateral EMI shield portion of the metal cage. The structure also includes a number of vias connecting a number of metal interconnect segments to the contacts. The metal interconnect segments form a top EMI shield portion of the metal cage.

US Patent:

20100283324, Nov 11, 2010

Filed:

Dec 11, 2009

Appl. No.:

12/636063

Inventors:

Dongyun Lee - Sunnyvale CA, US
Edward Pak - Saratoga CA, US
John Hahn - Los Altos CA, US
Mayank Gupta - Sunnyvale CA, US

Assignee:

SYNERCHIP CO., LTD. - Hsinchu

International Classification:

H02J 1/08

US Classification:

307 42

Abstract:

A system for delivering power over a network of devices connected through a serial link includes a first and second differential pairs of wires. Each differential pair of wires is double AC coupled by a HPF on one side and by another HPF on an opposite side. An LPF connects a portion of each differential pair of wires between the HPFs to a voltage source, and another LPF connects that portion of each differential pair to a load. The system further includes a third and fourth differential pairs of wires. All four differential pairs of wires are located within a single cable, such as a CAT6 cable. The first, second and third differential pair of wires are used for video links, and the fourth differential pair of wires are used for the bi-directional hybrid link. A power delivery circuit in each device includes a voltage source, a power relay switch, a signature resistor for detection, and a load detector.

US Patent:

20130191570, Jul 25, 2013

Filed:

Jan 12, 2011

Appl. No.:

13/521739

Inventors:

Dongyun Lee - Sunnyvale CA, US
Edward Pak - Saratoga CA, US
John Hahn - Los Altos CA, US
Mayank Gupta - Sunnyvale CA, US
Byoung Woon Kim - Cupertino CA, US
Paul Heninwolf - San Carlos CA, US
Sangwan Kim - Sunnyvale CA, US
Sukjae Cho - Santa Clara CA, US

Assignee:

SYNERCHIP CO., LTD. - HSINCHU CITY

International Classification:

G06F 13/42

US Classification:

710106

Abstract:

A system for delivering USB data over a DiiVA network may include a USB host controller, at least one USB device, a first DiiVA device connected to the USB host controller through an upstream USB port, a second DiiVA device connected to the USB device through a downstream USB port; and a network configured to transfer data between the first DiiVA device and the second DiiVA device according to USB protocol through a DiiVA bi-directional hybrid link in the network. The network is responsive to the USB host controller to deliver contents for the USB protocol through at least one line state information packet and at least one USB data packet transmitted through the hybrid link between the upstream USB port and the downstream USB port.

US Patent:

20130191872, Jul 25, 2013

Filed:

Jan 12, 2011

Appl. No.:

13/521762

Inventors:

Dongyun Lee - Sunnyvale CA, US
Edward Pak - Saratoga CA, US
John Hahn - Los Altos CA, US
Mayank Gupta - Sunnyvale CA, US
Byoung Woon Kim - Cupertino CA, US
Paul Heninwolf - San Carlos CA, US
Sangwan Kim - Sunnyvale CA, US
Sukjae Cho - Santa Clara CA, US

International Classification:

H04N 21/63

US Classification:

725 78

Abstract:

A system may include a video link and a hybrid link that connects a transmitting device to the receiving device, and at least one intermediate hop between the transmitting device and the receiving device. The intermediate hop may be configured to relay video content from the video source to the video sink through the hybrid link using one or more data relay modes. The hybrid link may be configured to perform hybrid link control signaling (HLCS) to manage a physical layer of the hybrid link. The video link between the video source and the video sink may be configured to transmit a video stream the from video source to the video sink over one or more video lanes. A video link training may be implemented for the video link and the hybrid link.

US Patent:

20140058889, Feb 27, 2014

Filed:

Aug 23, 2012

Appl. No.:

13/593193

Inventors:

Belinda Liu - Saratoga CA, US
Roshan Patel - San Ramon CA, US
Devarshi Vyas - San Jose CA, US
Xin Zhuang - Fremont CA, US
Mallikarjun Bhaigond - San Jose CA, US
Thennarasu Ponnusamy - Sunnyvale CA, US
Sree Gouri Pamarthy - San Jose CA, US
Thuy D. Nguyen - San Jose CA, US
Mayank Gupta - Milpitas CA, US
Venkateswar Goud Bathula - Cupertino CA, US

Assignee:

eBay Inc. - San Jose CA

International Classification:

G06Q 30/00
G06Q 30/06

US Classification:

705 268, 705 271

Abstract:

A system and method for a catalog item virtual fulfillment center is described. The system determines whether an item from a search query on an online marketplace corresponds to a catalog item. The catalog item corresponds to an item sold at substantially the same price among different sellers of the online marketplace. A display of a menu of different shipping times and corresponding total costs is generated for the catalog item.

US Patent:

60852712, Jul 4, 2000

Filed:

Apr 13, 1998

Appl. No.:

9/059615

Inventors:

Donald W. Smith - Santa Clara CA
Jack H. Choquette - Los Altos CA
Mayank Gupta - Sunnyvale CA

Assignee:

SandCraft, Inc. - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710113

Abstract:

A method and an apparatus using, in one embodiment, a multiple split mode for issuing multiple read or write requests that may be used during a data transaction within a computer system. In one embodiment, a processing unit comprises a bus arbitrator having bus control lines for controlling a bus, which transmits address and data information. The arbitrator is capable of issuing multiple consecutive read or write requests including at least one read request on the bus without releasing control by the processing unit over the bus during the consecutive read or write requests. In addition, the arbitrator is also designed to abort consecutive read requests during address cycles in response to bus control lines.