Maynard D Hammond

US Patent:

7298846, Nov 20, 2007

Filed:

Dec 4, 2000

Appl. No.:

09/729523

Inventors:

Kinney Bacon - Lawrenceville GA, US
Maynard Hammond - Lawrenceville GA, US

Assignee:

Scientific-Atlanta, Inc. - Lawrenceville GA

International Classification:

H04N 7/167

US Classification:

380212, 380200, 380210, 380240, 713193

Abstract:

In a subscriber television system with a host terminal, the present invention allows the identification of the individual packets from two separate MPEG transport streams that have been multiplexed together for decoding by a single external conditional access or point-of-deployment (POD) module. The decoding of individual packets from two separate MPEG transport streams supports the use of multiple tuner host terminals for such functions as picture-in-picture (PIP) program viewing and the viewing of one program while recording a second program.

US Patent:

7903815, Mar 8, 2011

Filed:

Oct 31, 2007

Appl. No.:

11/931701

Inventors:

Kinney Bacon - Lawrenceville GA, US
Maynard Hammond - Lawrenceville GA, US

International Classification:

H04N 7/167
H04L 9/00
H04L 9/12

US Classification:

380212, 380210, 380200, 380201, 380 33, 380240, 713193

Abstract:

In a subscriber television system with a host terminal, the present invention allows the identification of the individual packets from two separate MPEG transport streams that have been multiplexed together for decoding by a single external conditional access or point-of-deployment (POD) module. The decoding of individual packets from two separate MPEG transport streams supports the use of multiple tuner host terminals for such functions as picture-in-picture (PIP) program viewing and the viewing of one program while recording a second program.

US Patent:

60414170, Mar 21, 2000

Filed:

Jun 4, 1998

Appl. No.:

9/090440

Inventors:

Maynard D. Hammond - Lawrenceville GA
James M. Dewey - Ft. Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 112

US Classification:

713400

Abstract:

The present invention provides a method and apparatus for receiving and synchronizing data transmitted to a host interface unit of a graphics memory system on the rising and falling edges of a strobe signal in accordance with an accelerated graphics port (AGP) specification. An inner loop synchronization component, which is comprised in the host interface unit of the graphics memory system, receives data transmitted to the host interface unit on the falling and rising edges of a strobe signal and synchronizes the data to a PCI clock signal. The inner loop synchronization component comprises a first data transfer unit, a second data transfer unit and a control unit. The first data transfer unit comprises logic configured to capture the data transmitted on the falling edge of the strobe signal and to delay the captured data a predetermined number of cycles of the PCI clock before outputting the captured data from the first data transfer unit. The control unit detects the falling edge of the strobe signal and generates one or more timing signals based on the strobe signal. The rising edge of the strobe signal may or may not occur within the PCI clock cycle in which the falling edge of the strobe signal occurs.

US Patent:

60584386, May 2, 2000

Filed:

Feb 6, 1998

Appl. No.:

9/020190

Inventors:

Michael R. Diehl - Fort Collins CO
Maynard D. Hammond - Fort Collins CO
David L. McAllister - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1328

US Classification:

710 24

Abstract:

A system is provided for achieving high speed data transfers from a host memory to an ancillary processor, where the ancillary processor is preferably a geometry accelerator of a graphics machine. In accordance with a preferred embodiment, the system includes at least one memory segment having at least one enable bit and a starting address. The system further includes a data transfer queue defined in a portion of the host memory beginning at the starting location, where the data transfer queue has at least one header portion and at least one data portion, the header portion including at least one data ready bit that is indicative of whether the associated block of data is ready to be transferred to the ancillary processor. Finally, the system includes a controller, responsive to the enable bit, configured to transfer data directly from the data transfer queue to the ancillary processor, the controller being operative to evaluate the at least one data ready bit and transfer the associated block of data from the queue to the ancillary processor if the at least one data ready bit indicates that the data is ready for transfer.

US Patent:

62197258, Apr 17, 2001

Filed:

Aug 28, 1998

Appl. No.:

9/141801

Inventors:

Michael R. Diehl - Loveland CO
Maynard Hammond - Lawrenceville GA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1202
G06F 1200
G06F 1206
G06F 1300
G06F 900

US Classification:

710 26

Abstract:

A method and apparatus for transferring data in a computer system between a first memory region and second memory region in a single Direct Memory Access (DMA) operation. The first memory region, the second memory region, or both the first and second memory regions can include sub-regions of sequentially-addressable memory locations that are separated, within their respective regions, by a stride. The method and apparatus are particularly well adapted for use in computer graphics systems that include one or more regions of memory, such as frame buffers, that are organized in a rectangular manner as a plurality of contiguous but not sequentially-addressable memory locations within the memory of the graphics system.

US Patent:

56403887, Jun 17, 1997

Filed:

Dec 21, 1995

Appl. No.:

8/576637

Inventors:

Douglas F. Woodhead - Lawrenceville GA
Maynard D. Hammond - Lawrenceville GA
Richard A. Powers - Cumming GA
Paul Rimas Zalkauskas - Cumming GA

Assignee:

Scientific-Atlanta, Inc. - Norcross GA

International Classification:

H04L 1256

US Classification:

370468

Abstract:

In a system that transmits packets containing timestamps and information from a transmission site to a reception site at a transmission bit rate the packets may experience jitter, i. e. variable delay, during transmission. In such a case, the packets are temporally shifted relative to the timestamps and to other packets. Where the timestamp values are inserted into selected packets prior to transmission and that timestamp represent the value of the transmission site clock, the method and apparatus of the present invention substantially removes the jitter and adjusts the timestamp values prior to reception of the packets at the reception site. The present invention achieves this goal by receiving the packets at an intermediate site that has a local clock operates at a nominal frequency substantially equal to the nominal frequency of the transmission site clock and uses that clock as a jitter-free clock to correct the packets. The packets are stored in a buffer at the intermediate site and output from the buffer at a controlled rate to maintain a substantially constant average transit time of packets through the buffer. Before the packets are output for reception at the reception site the timestamps of selected packets are modified to reflect the new temporal relationship between packets due to the controlled rate of output from the intermediate site.

US Patent:

54673429, Nov 14, 1995

Filed:

Oct 5, 1994

Appl. No.:

8/318124

Inventors:

Gary L. Logston - Tucker GA
Anthony J. Wasilewski - Alpharetta GA
Maynard Hammond - Lawrenceville GA
Francis Cheung - Tucker GA

Assignee:

Scientific-Atlanta, Inc. - Atlanta GA

International Classification:

H04J 316
H04L 1256
H04Q 1104

US Classification:

370 17

Abstract:

Packets of data, some of which may carry a timestamp value, are transmitted through an Asynchronous Transfer Mode (ATM) network. Prior to transmission, each packet of data is encapsulated in a respective convergence sublayer protocol data unit (CS-PDU) having a header portion and a payload portion. The header portion of each CS-PDU contains a time correction indicator (TCI), which indicates whether the CS-PDU carries a packet of data having a timestamp value that may require correction after the CS-PDU passes through the network, and a time reference correction (TRC) field. Each CS-PDU is then segmented into a plurality of successive segments; a first one of the segments of each CS-PDU contains the CS-PDU header. Each segment is then inserted into the payload section of a respective ATM cell for transmission through the network. At each node in the network, cells are examined to determine if they contain a CS-PDU header.

US Patent:

20150071300, Mar 12, 2015

Filed:

Sep 12, 2013

Appl. No.:

14/025607

Inventors:

- Coppell TX, US
- San Jose CA, US
Jonathan EVANS - Dunwoody GA, US
Maynard Darvel HAMMOND - Lawrenceville GA, US
Zhifang J. NI - PLANO TX, US
Charaf HANNA - Lewisville TX, US

Assignee:

Cisco Technology, Inc. - San Jose CA
STMicroelectronics, Inc. - Coppell TX

International Classification:

H04L 12/823
H04L 12/873

US Classification:

370412

Abstract:

A system and method suited for improved overall data transmission having a hardware-based transceiver configured for transmitting upstream data with suppressed data packets. In TCP sessions between devices, a server seeks an “acknowledgement” that the downstream data transmission has been received by a client. Some data packets sent upstream may contain only TCP acknowledgement data and therefore may be combined with other purely TCP acknowledgement data packets in order to reduce the impact of the TCP acknowledgement packets on the overall upstream data throughput. In addition, this results in increased TCP performance in the downstream transmission direction as well because the algorithm enables replacing earlier arriving ACK packets with later arriving ACK packets which allows the device to send all TCP ACK information known to the suppressor at the earliest possible time.