Mehdi H Sani

US Patent:

6429904, Aug 6, 2002

Filed:

Feb 13, 2001

Appl. No.:

09/783068

Inventors:

Mehdi H. Sani - San Diego CA
De Dzwo Hsu - San Diego CA
Willard K. Bucklen - Greensboro NC

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H03M 112

US Classification:

348572, 348573, 341155

Abstract:

A VGA to analog video converter is useful e. g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.

US Patent:

6615027, Sep 2, 2003

Filed:

Jan 21, 2000

Appl. No.:

09/489231

Inventors:

Gurkanwal Sahota - San Diego CA
Mehdi H. Sani - San Diego CA
Sassan Shahrokhinia - San Diego CA

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H04B 102

US Classification:

455 91, 455 93, 341126, 341135, 341144

Abstract:

Circuitry that generates an interface signal between a first and a second integrated circuit (IC). The circuitry includes a reference circuit that provides a reference signal, an interface circuit, and a circuit element. The interface circuit is implemented on the first IC, operatively couples to the reference circuit, receives the reference signal and a data input, and generates the interface signal. The circuit element is implemented on the second IC, operatively couples to the control circuit, receives the interface signal, and provides an output signal. The reference signal can be a voltage or a current signal, and can be generated in the first or second IC. The interface circuit can be implemented with a current mirror coupled to a switch array, and can be oversampled to ease the filtering requirement. The interface signal can be a differential current signal having multiple (e. g. , four, eight, or more) bits of resolution.

US Patent:

6794914, Sep 21, 2004

Filed:

May 24, 2002

Appl. No.:

10/155378

Inventors:

Mehdi Hamidi Sani - San Diego CA
Gregory A. Uvieghara - San Diego CA

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H03K 3289

US Classification:

327202, 327203

Abstract:

An integrated circuit including a Multi-Threshold CMOS (MTCMOS) latch combining low voltage threshold CMOS circuits with high voltage threshold CMOS circuits. The low voltage threshold circuits including a majority of the circuits in the signal path of the latch to ensure high performance of the latch. The latch further including high voltage threshold circuits to eliminate leakage paths from the low voltage threshold circuits when the latch is in a sleep mode. A single-phase latch and a two-phase latch are provided. Each of the latches is implemented with master and slave registers. Data is held in either the master register or the slave register depending on the phase or phases of the clock signals. A multiplexer may alternatively be implemented prior to the master latch for controlling an input signal path during sleep and active modes of the latch and for providing a second input signal path for test.

US Patent:

6950359, Sep 27, 2005

Filed:

Mar 28, 2003

Appl. No.:

10/403101

Inventors:

Nan Chen - San Diego CA, US
Cheng Zhong - San Diego CA, US
Mehdi Hamidi Sani - San Diego CA, US

Assignee:

Qualcomm Inc. - San Diego CA

International Classification:

G11C007/00

US Classification:

365203, 365154, 365206

Abstract:

Techniques for replacing and eliminating paths causing channel leakage current. In one embodiment, one or more precharge enable transistors and a precharge enable signal are added to a circuit configuration. The precharge enable transistors are designed to remain on and simply pass a signal in a properly functioning path. When a leakage path is identified, such as during IDDQ testing, the precharge enable signal is set to turn off the precharge enable transistors. When the precharge enable transistors are off, the leakage path is disrupted, and the leakage current stopped. The path may be replaced with a redundant path.

US Patent:

6975362, Dec 13, 2005

Filed:

May 13, 2002

Appl. No.:

10/145285

Inventors:

Mehdi H. Sani - San Diego CA, US
De Dzwo Hsu - San Diego CA, US
Willard K. Bucklen - Greensboro NC, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H04N007/01
H04N011/20

US Classification:

348446, 348447, 345603

Abstract:

A VGA to analog video converter is useful e. g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.

US Patent:

7092307, Aug 15, 2006

Filed:

Aug 14, 2003

Appl. No.:

10/641883

Inventors:

Nan Chen - San Diego CA, US
Cheng Zhong - San Diego CA, US
Mehdi Hamidi Sani - San Diego CA, US

Assignee:

Qualcomm Inc. - San Diego CA

International Classification:

G11C 5/14

US Classification:

365226, 365229

Abstract:

A CMOS integrated circuit (e. g. , an SRAM or a DRAM) is partitioned into a core block, a peripheral block, and a retention block. The core block includes circuits (e. g. , memory cells) that are powered on at all times and is coupled directly to power supply and circuit ground. The peripheral block includes circuits that may be powered on or off and are coupled to the power supply via a head switch and/or to circuit ground via a foot switch. The switches and the core block may be implemented with high threshold voltage (high-Vt) FET devices to reduce leakage current. The peripheral block may be implemented with low-Vt FET devices for high-speed operation. The retention block includes circuits (e. g. , pull-up devices) that maintain signal lines (e. g. , word lines) at a predetermined level so that the internal states of the core block are retained when the peripheral block is powered off.

US Patent:

7471110, Dec 30, 2008

Filed:

Mar 23, 2006

Appl. No.:

11/389332

Inventors:

Abhay Dixit - San Diego CA, US
Mehdi Hamidi Sani - Rancho Santa Fe CA, US
Vivek Mohan - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03K 19/094

US Classification:

326 83, 326 87

Abstract:

A transceiver interface for data transfer between two integrated circuits (ICs or “chips”) utilizes a current mode technique rather than conventional voltage mode differential signaling techniques. A current pulse is injected into one of two transmission wires based on a signal value to be transmitted (e. g. , logic “0” or “1”) by a driver on a transmitting chip. The current pulse is received as a differential current signal at a receive block in a receiving chip. The differential signal is converted to a low swing differential voltage signal by current comparators. The differential voltage signal may be detected by an op-amp receiver which outputs the appropriate signal value.

US Patent:

7764537, Jul 27, 2010

Filed:

Jan 11, 2008

Appl. No.:

11/972674

Inventors:

Seong-Ook Jung - Seoul, KR
Seung H. Kang - San Diego CA, US
Sei Seung Yoon - San Diego CA, US
Mehdi Hamidi Sani - Rancho Santa Fe CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 11/00

US Classification:

365158, 365161, 365171, 365173

Abstract:

Systems, circuits and methods for determining read and write voltages for a given word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region of the word line transistor. A second voltage, which is less than the first voltage, can be supplied for read operations so that the read operations occur in the linear region of the word line transistor.