Mehmet S Ozturk

US Patent:

6709929, Mar 23, 2004

Filed:

Jun 24, 2002

Appl. No.:

10/178941

Inventors:

Zhibo Zhang - Raleigh NC
Veena Misra - Raleigh NC
Salah M. A. Bedair - Raleigh NC
Mehmet Ozturk - Cary NC

Assignee:

North Carolina State University - Raleigh NC

International Classification:

H01L 21336

US Classification:

438268, 206962, 257 14, 205324

Abstract:

Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

US Patent:

6914256, Jul 5, 2005

Filed:

Jan 20, 2004

Appl. No.:

10/760966

Inventors:

Zhibo Zhang - Raleigh NC, US
Veena Misra - Raleigh NC, US
Salah M. A. Bedair - Raleigh NC, US
Mehmet Ozturk - Cary NC, US

Assignee:

North Carolina State University - Raleigh NC

International Classification:

A01L029/06
C23C028/00

US Classification:

257 15, 257 9, 257 14, 257 18, 257 28, 257 37, 205201

Abstract:

Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

US Patent:

7211458, May 1, 2007

Filed:

Aug 8, 2005

Appl. No.:

11/199313

Inventors:

Mehmet Ozturk - Cary NC, US
Veena Misra - Raleigh NC, US
Saurabh Chopra - Raleigh NC, US

Assignee:

North Carolina State University - Raleigh NC

International Classification:

H01L 21/00
H01L 29/04
H01L 27/148

US Classification:

438 36, 438 37, 438 46, 438 87, 257 63, 257219, 257223

Abstract:

A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.

US Patent:

7265375, Sep 4, 2007

Filed:

Feb 24, 2005

Appl. No.:

11/065085

Inventors:

Zhibo Zhang - Raleigh NC, US
Veena Misra - Raleigh NC, US
Salah M. A. Bedair - Raleigh NC, US
Mehmet Ozturk - Cary NC, US

Assignee:

North Carolina State University - Raleigh NC

International Classification:

H01L 29/12

US Classification:

257 15, 257E29071, 977762

Abstract:

Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

US Patent:

52504522, Oct 5, 1993

Filed:

Jun 19, 1991

Appl. No.:

7/717631

Inventors:

Mehmet Ozturk - Cary NC
Jimmie Wortman - Chapel Hill NC

Assignee:

North Carolina State University - Raleigh NC

International Classification:

H01L 21441

US Classification:

437 41

Abstract:

The invention is a method of depositing a layer of polycrystalline silicon on a silicon dioxide substrate until the layer of polycrystalline silicon is thick enough to support the deposition of germanium thereon, but while thin enough to substantially avoid the deleterious effects on the characteristics of semiconductor device structure that the deposition of polycrystalline silicon would otherwise potentially cause. The polycrystalline layer is then exposed to a germanium containing gas at a temperature below the temperature at which germanium will deposit on silicon dioxide alone while preventing native growth of silicon dioxide on the polycrystalline silicon layer, and for a time sufficient for a desired thickness of polycrystalline germanium to be deposited on the layer of polycrystalline silicon.

US Patent:

53369033, Aug 9, 1994

Filed:

May 28, 1993

Appl. No.:

8/069030

Inventors:

Mehmet C. Ozturk - Cary NC
Douglas T. Grider - Pleasanton CA
Mahesh K. Sanganeria - Raleigh NC
Stanton P. Ashburn - Cary NC
Jimmie J. Wortman - Chapel Hill NC

Assignee:

North Carolina State University at Raleigh - Raleigh NC

International Classification:

H01L 2348

US Classification:

257 19

Abstract:

Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.

US Patent:

54398509, Aug 8, 1995

Filed:

Sep 8, 1993

Appl. No.:

8/117870

Inventors:

Mehmet C. Ozturk - Cary NC
Mahesh K. Sanganeria - Raleigh NC

Assignee:

North Carolina State University - Raleigh NC

International Classification:

H01L 2100

US Classification:

437228

Abstract:

A ring is provided on a monocrystalline silicon wafer at one face thereof and adjacent the edge thereof. The ring increases the optical absorptivity of the wafer adjacent the ring compared to the optical absorptivity of the wafer distant from the ring. The ring therefore at least partially compensates for edge cooling of the wafer during rapid thermal processing thereof. Uniform thickness layers can therefore be deposited on a wafer in a rapid thermal processing system. When depositing polycrystalline silicon on an oxide covered layer, the ring may be formed as a circular trench in the oxide layer adjacent the wafer edge.

US Patent:

51622467, Nov 10, 1992

Filed:

Nov 8, 1991

Appl. No.:

7/790230

Inventors:

Mehmet Ozturk - Cary NC
Jimmie Wortman - Chapel Hill NC
Douglas Grider - Raleigh NC

Assignee:

North Carolina State University - Raleigh NC

International Classification:

H01L 21265

US Classification:

437 41

Abstract:

The invention is a method of selectively forming contacts on ultra shallow source and drain junctions. The method comprises forming a gate structure that defines a gate on a silicon substrate, portions of which are covered with a layer of silicon dioxide while the portions adjacent the gate form a silicon surface. The gate structure includes a surface material upon which germanium will not deposit at a temperature that is otherwise high enough to cause germanium to deposit from a germanium containing gas onto a silicon surface, but that is lower than the temperature at which germanium will deposit on the gate surface material. A source and drain are formed in the silicon substrate in the portions adjacent the gate by adding dopant atoms and in which the source and drain are separated by an active region of the silicon substrate defined by the gate structure. The substrate is then exposed to a germanium containing gas at a temperature high enough to cause the germanium to deposit from the germanium containing gas onto the silicon surface but lower than the temperature at which the germanium will deposit on the gate structure surface material. The result is self-aligned germanium contacts to the source and the drain.