Melissa Ann Barnum

US Patent:

7467277, Dec 16, 2008

Filed:

Feb 7, 2006

Appl. No.:

11/348879

Inventors:

Melissa Ann Barnum - Kasson MN, US
Mark David Bellows - Rochester MN, US
Paul Allen Ganfield - Rochester MN, US
Lonny Lambrecht - Byron MN, US
Tolga Ozguner - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/14

US Classification:

711167, 711158, 713322, 713600

Abstract:

The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

US Patent:

7676639, Mar 9, 2010

Filed:

Feb 21, 2008

Appl. No.:

12/034681

Inventors:

Melissa Ann Barnum - Kasson MN, US
Paul Allen Ganfield - Rochester MN, US
Lonny Lambrecht - Byron MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711155, 711105, 711167, 710 52, 36518905

Abstract:

Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

US Patent:

7716430, May 11, 2010

Filed:

Feb 20, 2008

Appl. No.:

12/033910

Inventors:

Melissa Ann Barnum - Kasson MN, US
Paul Allen Ganfield - Rochester MN, US
Lonny Lambrecht - Byron MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711155, 711105, 711167, 36518905, 714 54, 714764

Abstract:

Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

US Patent:

7761682, Jul 20, 2010

Filed:

Aug 13, 2008

Appl. No.:

12/191195

Inventors:

Melissa Ann Barnum - Kasson MN, US
Mark David Bellows - Rochester MN, US
Paul Allen Ganfield - Rochester MN, US
Lonny Lambrecht - Byron MN, US
Tolga Ozguner - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/14
G06F 13/36

US Classification:

711167, 711168, 711169

Abstract:

The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

US Patent:

7363442, Apr 22, 2008

Filed:

Nov 12, 2004

Appl. No.:

10/988314

Inventors:

Melissa Ann Barnum - Kasson MN, US
Paul Allen Ganfield - Rochester MN, US
Lonny Lambrecht - Byron MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711155, 711105, 711167, 36518905, 710 52

Abstract:

A method, an apparatus, and a computer program are provided for the separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

US Patent:

20060107001, May 18, 2006

Filed:

Nov 12, 2004

Appl. No.:

10/988311

Inventors:

Melissa Barnum - Kasson MN, US
Kent Haselhorst - Byron MN, US
Lonny Lambrecht - Byron MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

711154000

Abstract:

An arbitration structure, a method, and a computer program are provided for an arbitration scheme that can handle a plurality of memory commands in an operating system. Typically, in a memory system there are three types of memory commands: periodic, read, and write. An arbitration scheme determines the order of priority in which these commands are executed. This arbitration scheme is flexible because it contains a read/write priority module, which can be programmed to execute any order of priority combination of read and write commands. This enables an arbitration scheme for any memory system to be easily programmed for maximum efficiency.

US Patent:

20070220361, Sep 20, 2007

Filed:

Feb 3, 2006

Appl. No.:

11/347415

Inventors:

Melissa Barnum - Kasson MN, US
Lonny Lambrecht - Byron MN, US
Tolga Ozguner - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 11/00

US Classification:

714045000

Abstract:

The present invention provides a way to offload trace data from a processor and store the trace data in external memory. By accumulating trace data in large buffers and sending them to a memory interface controller, the memory interface controller may write trace data to memory as the memory interface controller would execute a normal write to memory. In this manner, no additional I/O memory pins are required and processor memory storage for trace data is kept to a minimum. Furthermore, by using a special port to the memory interface controller the writing of trace data may be accomplished in a manner that does not affect the speed of the on-chip bus between the processor and the memory interface controller.

US Patent:

20070250283, Oct 25, 2007

Filed:

Apr 25, 2006

Appl. No.:

11/380025

Inventors:

Melissa Barnum - Kasson MN, US
Mark Bellows - Rochester MN, US
Lonny Lambrecht - Byron MN, US

International Classification:

G06F 19/00

US Classification:

702117000, 702085000, 702107000, 702108000, 714047000, 714718000

Abstract:

Embodiments of the present invention provide methods, systems and apparatus for performing memory maintenance and calibration operations. To perform calibration operations, calibration data may first be written to memory, and subsequently read back. The calibration operations may then be performed in response to detecting discrepancies between the data written and data read back from memory. To prevent the calibration data from being altered during memory maintenance operations, embodiments of the invention provide for the skipping of sections containing calibration data during the memory maintenance operations. Therefore, the calibration data is preserved, allowing for appropriate calibration operations to be performed.