Melvin Wesley Marmet

US Patent:

46927174, Sep 8, 1987

Filed:

Dec 8, 1986

Appl. No.:

6/940212

Inventors:

Kenneth W. Ouyang - Huntington Beach CA
Melvin Marmet - Placentia CA

Assignee:

Western Digital Corporation - Irvine CA

International Classification:

H03K 3023
H03K 3354

US Classification:

331111

Abstract:

A CMOS voltage controlled oscillator includes a reference capacitor which is charged and discharged by current source and sink output transistors. The output transistors are connected to control transistors in a current mirror fashion with current through the control transistors being maintained at a level proportional to the value of a control input voltage. The control transistors are selectively connected to the output transistors in a current mirror configuration to provide either current source or sink operation. Transmission gates are connected between the gates of the output and control transistors and selectively closed to render the proper output transistor conductive to achieve source or sink operation. MOS capacitors are connected to the control transistors to facilitate rapid switching of the output transistors to enable high frequency operation of the voltage controlled oscillator.

US Patent:

50518607, Sep 24, 1991

Filed:

May 12, 1989

Appl. No.:

7/351670

Inventors:

Kowk Fai V. Lee - Irvine CA
Alan Lee - Irvine CA
Melvin L. Marmet - San Clemente CA
Kenneth W. Ouyang - Huntington Beach CA

Assignee:

Western Digital Corporation - Irvine CA

International Classification:

H02H 904

US Classification:

361 58

Abstract:

An electrostatic discharge protection circuit employing an extended resistive structure having bimodal resistance characteristics in series with an input/output buffer circuit and an input/output electrical contact pad on an integrated circuit. The extended resistive structure is integrally formed with the device or devices in the buffer circuit most susceptible to damage due to ESD breakdown effects. In a first resistance mode during normal circuit operations, the resistor has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistor has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. Thick oxide snap-back device is also employed to provide a parallel ESD discharge path with low power dissipation.

US Patent:

43552471, Oct 19, 1982

Filed:

Feb 11, 1980

Appl. No.:

6/120239

Inventors:

Melvin L. Marmet - Norco CA

Assignee:

Rockwell International Corporation - El Segundo CA

International Classification:

H03K 518

US Classification:

307530

Abstract:

A circuit for producing a signal of one type in the absence of a semiconductor at an addressed memory location and a signal of another type in the presence of the semiconductor includes a constant voltage reference source to supply a variable current to a pull up FET. The pull up FET is connected to be in series with the memory semiconductor when it is present in the circuit, and operates to supply a low level voltage to an output amplifier when the semiconductor is present and a high level voltage when the semiconductor is not present. The low level voltage is centered about the trigger point of the amplifier, so that the bit line swing from the memory semiconductor produces a full MOS output from the amplifier.

US Patent:

42741475, Jun 16, 1981

Filed:

Sep 4, 1979

Appl. No.:

6/072383

Inventors:

Clarence W. Padgett - Westminster CA
Melvin L. Marmet - Corona CA
Mark R. Tennyson - Anaheim CA

Assignee:

Rockwell International Corporation - El Dequndo CA

International Classification:

G11C 700
G11C 706

US Classification:

365189

Abstract:

A static read only memory fabricated with field effect transistors of either the depletion type or the enhancement type connected in series. The read only memory includes a compact sensing circuit for detecting relatively small voltage swings at each node corresponding to a bit line of the memory cell, and a highly sensitive differential sense amplifier including first and second cascaded connected inverter stages.

US Patent:

42322707, Nov 4, 1980

Filed:

Jun 14, 1979

Appl. No.:

6/048559

Inventors:

Melvin L. Marmet - Corona CA
Clarence W. Padgett - Westminster CA

Assignee:

Rockwell International Corporation - Segundo CA

International Classification:

H03F 345
H03F 316

US Classification:

330253

Abstract:

An improved high gain, field effect transistor differential amplifier including first and second cascade connected inverter stages, a feedback controlled source of current connected to each of the stages, including a source of controlled positive feedback for increasing the voltage gain. A positive feedback path is connected between an output terminal of the differential amplifier and the source of current so that the current in each inverter stage is more precisely controlled.

US Patent:

41033493, Jul 25, 1978

Filed:

Jun 16, 1977

Appl. No.:

5/807460

Inventors:

Melvin L. Marmet - Corona CA

Assignee:

Rockwell International Corporation - El Segundo CA

International Classification:

G11C 802

US Classification:

365231

Abstract:

A Y address decoder used in conjunction with an X-Y matrix array, high density read-only memory unit, that reduces the number of series FET stages in the electrical path needed to evaluate the logic state of an addressed cell location of such a read-only memory unit. The reduction is achieved by gating logic in which the signal stored in the evaluated cell location, is derived from the output terminals of a tier of decoders, the appropriate decoder being connected directly to an output driver by a gate-controlled switch. The gate signal to render each such switch conductive is generated by an AND-OR circuit in repsonse to a unique Y address code, thereby obviating the otherwise time-consuming requirement for the evaluation signal to flow through additional tiers of decoders.

US Patent:

47178400, Jan 5, 1988

Filed:

Mar 14, 1986

Appl. No.:

6/839501

Inventors:

Kenneth W. Ouyang - Huntington Beach CA
Melvin Marmet - Norco CA

Assignee:

Western Digital Corporation - Irvine CA

International Classification:

H03K 1722

US Classification:

307594

Abstract:

A power-up reset circuit for providing a reset signal for resetting circuit elements such as flip-flops upon the application of power to the circuit includes a CMOS pair output section and a capacitor coupled to the gates of the CMOS transistors. The capacitor is charged up by the power supply to switch the reset signal to a low level after the resetting operation has been achieved. In order to accommodate slow ramping power supplies, circuitry operating as a voltage sensitive switch is included to prevent the capacitor from charging until the power supply voltage has reached a sufficient level to ensure proper operation. In order to accommodate fast ramping power supplies, the charging rate of the capacitor is controlled to assure a minimum necessary duration of the reset signal.

US Patent:

52705650, Dec 14, 1993

Filed:

May 30, 1991

Appl. No.:

7/708790

Inventors:

Kwok Fai V. Lee - Irvine CA
Alan Lee - Irvine CA
Melvin L. Marmet - San Clemente CA
Kenneth W. Ouyang - Huntington Beach CA

Assignee:

Western Digital Corporation - Irvine CA

International Classification:

H01L 2906
H01L 2978
H01L 2702

US Classification:

257358

Abstract:

An electrostatic discharge protection circuit employing an extended resistive structure having bimodal resistance characteristics in series with an input/output buffer circuit and an input/output electrical contact pad on an integrated circuit. The extended resistive structure is integrally formed with the device or devices in the buffer circuit most susceptible to damage due to ESD breakdown effects In a first resistance mode during normal circuit operations, the resistor has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistor has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. Thick oxide snap-back device is also employed to provide a parallel ESD discharge path with low power dissipation.