Mervyn Jacie W Wong

US Patent:

6620682, Sep 16, 2003

Filed:

Oct 16, 2001

Appl. No.:

09/978230

Inventors:

Peter W. Lee - Saratoga CA
Hsing-Ya Tsao - San Jose CA
Fu-Chang Hsu - San Jose CA
Mervyn Wong - El Cerrito CA

Assignee:

Aplus Flash Technology, Inc. - San Jose CA

International Classification:

H01L 21336

US Classification:

438257, 438 14, 438 61

Abstract:

In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

US Patent:

6777292, Aug 17, 2004

Filed:

Jul 25, 2003

Appl. No.:

10/627183

Inventors:

Peter W. Lee - Saratoga CA
Hsing-Ya Tsao - San Jose CA
Fu-Chang Hsu - San Jose CA
Mervyn Wong - El Cerrito CA

Assignee:

Aplus Flash Technology, Inc. - San Jose CA

International Classification:

H01L 21336

US Classification:

438257, 438 14, 438 61, 365185

Abstract:

In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

US Patent:

20040029335, Feb 12, 2004

Filed:

Jul 25, 2003

Appl. No.:

10/627834

Inventors:

Peter Lee - Saratoga CA, US
Hsing-Ya Tsao - San Jose CA, US
Fu-Chang Hsu - San Jose CA, US
Mervyn Wong - El Cerrito CA, US

Assignee:

APLUS FLASH TECHNOLOGY, INC.

International Classification:

H01L021/8238

US Classification:

438/200000

Abstract:

In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

US Patent:

6556481, Apr 29, 2003

Filed:

May 9, 2001

Appl. No.:

09/852247

Inventors:

Fu-Chang Hsu - San Jose CA
Hsing-Ya Tsao - San Jose CA
Peter W. Lee - Saratoga CA
Mervyn Wong - El Cerrito CA

Assignee:

Aplus Flash Technology, Inc. - San Jose CA

International Classification:

G11C 1604

US Classification:

36518524, 3651852, 36518528, 36518529

Abstract:

In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a plurality of cell types to produce a symmetrical design and allowing shrinkage of the cell beyond that which is possible with other cells designed to use a two step write procedure. The methodology can be applied to either N-channel or P-channel devices and can be used on various type memory cells such as âETOXâ, âNORâ type, âANDâ type, and âORâ type. Erasing and programming steps increase the Vt of the cell transistor, whereas reverse programming decreases the Vt of the cell transistor. Over-erase problems are eliminated using the three step write procedure.