Michael G Alexander

Address:

11915 Stonehollow Dr APT 422, Austin, TX 78758

Phone:

9153337160

VIN:

JTDBT923271115439

Make:

TOYOTA

Model:

YARIS

Year:

2007

US Patent:

8117399, Feb 14, 2012

Filed:

May 7, 2009

Appl. No.:

12/437115

Inventors:

David F. Greenberg - Austin TX, US
Michael C. Alexander - Austin TX, US
Kathryn C. Stacer - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 12/08

US Classification:

711141, 711125

Abstract:

Each cacheline of a unified cache storing information is marked as incoherent if the information was acquired incoherently or marked as coherent if the information was acquired coherently. A subsequent incoherent read access to a cacheline can result in a cache hit and a return of the cached information regardless of whether the cacheline is marked as coherent or incoherent. However, a subsequent coherent read access to a cacheline marked as incoherent will be returned as a cache miss regardless of whether the cacheline includes information sought by the coherent read access. In response to a cache miss for a coherent read access, a global snoop is initiated so as to query all other target components within the same coherency domain. In contrast, a cache miss resulting from an incoherent read access is processed using a non-global snoop to a limited set of one or a few target components in the coherency domain.

US Patent:

20130230248, Sep 5, 2013

Filed:

Mar 2, 2012

Appl. No.:

13/411243

Inventors:

Michael G. Alexander - Austin TX, US
Paul R. Bastide - Boxford MA, US
Matthew E. Broomhall - South Burlington VT, US
Beth Anne M. Collopy - Amesbury MA, US
Robert E. Loredo - North Miami Beach FL, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16
G06K 9/18

US Classification:

382182, 709205

Abstract:

A method, system and computer program product for ensuring that the tags accurately describe a resource referenced by a bookmark in a collaborative bookmarking system. A user bookmarking an Internet resource that is referenced by a bookmark is detected. The user provides a description of the bookmark in the form of metadata, which includes tags, to be associated with the bookmark. The Internet resource is analyzed to determine its meaning. A second user bookmarking the same Internet resource that is referenced by the bookmark is detected. The second user provides a description of the bookmark in the form of metadata, which includes tags. The Internet resource is analyzed a second time to determine its meaning If the relatedness of these meanings is beyond a threshold limit, then the original bookmark metadata is invalidated and the invalidated tags are replaced with the tags provided by the second user.

US Patent:

57427992, Apr 21, 1998

Filed:

Feb 18, 1997

Appl. No.:

8/801648

Inventors:

Michael Alexander - Austin TX
Carmine Nicoletta - Austin TX
Arthur R. Piejko - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 112

US Classification:

395552

Abstract:

A method and apparatus for synchronizing multiple busses having different cycle times in a data processing system (10). The present invention synchronizes multiple clocks having different phase and frequencies without redundant use of phase lock loop units. An initial unit (7) receives an external system clock having an initial phase and frequency. An internal clock (112) is generated which is a phase and frequency adjusted derivation of the system clock. From this internal clock (112) a global clock (101) for use within the data processor (10) is generated. A second unit (9) receives the internal clock (112) and performs phase adjustment to provide a peripheral clock (114). The provision of the internal clock (112) detaches the dependency of peripheral clock (114) generation from the global clock (101), while maintaining a phase relationship with the global clock (101). In one embodiment, the present invention is implemented without the costly use of multiple phase lock loops.

US Patent:

44357036, Mar 6, 1984

Filed:

Jul 6, 1981

Appl. No.:

6/280613

Inventors:

Glenn E. Hunt - Austin TX
Michael C. Alexander - Austin TX
Gerald L. Lozano - Austin TX
Gerald O. Manktelow - Austin TX

Assignee:

Data General Corporation - Westboro MA

International Classification:

G09G 116

US Classification:

340723

Abstract:

Apparatus and method for simultaneous display of alphanumeric characters of variable character density on a raster scan CRT monitor is disclosed. Circuitry is provided to supply multiple sources of timing for terminal operations, to switch among timing sources without display degradation, and to vary the number of dots per raster line that constitute a character field. The density of displayed characters may be changed, under user control, for each character row.

US Patent:

57817650, Jul 14, 1998

Filed:

Nov 3, 1995

Appl. No.:

8/552657

Inventors:

Michael C. Alexander - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 104

US Classification:

395551

Abstract:

A system for data synchronization in a bus interface unit (12) controls the flow of data between data processor (10) operating at a higher clock rate and the address and data buses operating at a lower clock rate. The data synchronization system incorporates circuit paths operating in four different clock domains: core-rate, bus-rate, transfer-rate, and receive-rate. Circuits processing data solely at the higher clock rate of the data processor or the lower clock rate of the address and data buses operate in the core-rate or bus-rate domains, respectively. The transfer-rate domain is used to transfer data from the core-rate to the bus-rate. Conversely, the receive-rate domain is used to transfer data from the bus-rate to the core-rate. The data synchronization system provides a general solution to the problem unreliable half cycle data paths.

US Patent:

60290064, Feb 22, 2000

Filed:

Dec 23, 1996

Appl. No.:

8/772713

Inventors:

Michael Alexander - Austin TX
Belliappa Kuttanna - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 132

US Classification:

39575005

Abstract:

A data processor (10) incorporates instruction regulating or "throttling" circuitry (31) for limiting consumed power. A user visible register maintains an INTERVAL field by which instruction fetch from an instruction cache (14) is periodically delayed. This INTERVAL field may be adjusted to suit the power budget of the data processor.

US Patent:

54208084, May 30, 1995

Filed:

May 13, 1993

Appl. No.:

8/061397

Inventors:

Michael C. Alexander - Austin TX
Arturo L. Arizpe - Buda TX
Gianfranco Gerosa - Austin TX
James A. Kahle - Austin TX
Aubrey D. Ogden - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL

International Classification:

G06F 132

US Classification:

364707

Abstract:

A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.

US Patent:

44464576, May 1, 1984

Filed:

Jul 6, 1981

Appl. No.:

6/280612

Inventors:

Michael C. Alexander - Austin TX

Assignee:

Data General Corporation - Westboro MA

International Classification:

G09G 116

US Classification:

340745

Abstract:

A raster scan CRT character generator comprising a memory having dot patterns for a plurality alphanumeric characters stored therein and a multiplexer, controlled by a signal from the memory, for selecting one of a plurality of sets of inputs to be used for determining the state of dots in the character field other than the character dot pattern.