Michael F Anthony

US Patent:

6381197, Apr 30, 2002

Filed:

Mar 8, 2000

Appl. No.:

09/521393

Inventors:

Bernard J Savord - Andover MA 01810
William J Ossmann - Acton MA 01720
Jie Chen - North Andover MA 01845
Michael P Anthony - Andover MA 01810
Turuvekere R Gururaja - Parkvale Drive Discovery Bay, HK
Stephen M Grenon - Hillsborough NC 27278

International Classification:

H04R 1700

US Classification:

367178

Abstract:

A micro-machined ultrasonic transducer (MUT) having aperture, elevation and apodization controlled by apparatus located on the same substrate as the transducer, or by bias voltage control applied to MUT elements, allows for an efficient and compact ultrasonic probe. The control apparatus may take the form of field effect transistors (FETs), micro-machined relays, or doped regions on the substrate, or any other apparatus that may be located on the same substrate as that of the transducer, or by bias voltage sources connected to the MUT elements.

US Patent:

6500120, Dec 31, 2002

Filed:

Jul 31, 2001

Appl. No.:

09/919524

Inventors:

Michael P. Anthony - Andover MA

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

A61B 800

US Classification:

600437, 600443

Abstract:

A simple, low cost ultrasound beamforming system uses an analog random access memory (RAM) element for each beamforming channel. The system includes a processor and an ultrasonic transducer array. The ultrasonic transducer array includes a plurality of transducer elements, each transducer element associated with one of a plurality of channels. The system also includes a beamformer adapted to receive an output signal from each of the plurality of transducer elements, and a delay element located in the beamformer and associated with each of the channels, where the delay element comprises an analog random access memory element.

US Patent:

6705995, Mar 16, 2004

Filed:

Oct 4, 2002

Appl. No.:

10/264900

Inventors:

McKee Dunn Poland - Andover MA
Bernard J. Savord - Andover MA
Michael P. Anthony - Andover MA

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

A61B 800

US Classification:

600447

Abstract:

A phased array ultrasound scanning apparatus includes a one-dimensional (1-D) array of ultrasound transducer elements having transmit and receive elements. The 1-D array is responsive to a transmitter configured to energize the transmit elements for generating a transmit acoustic beam directed into a region of interest. A receive beamformer, operatively connected to the 1-D array, synthesizes receive beams, in response to echoes of the transmit acoustic beam received from the region of interest. The receive beamformer includes analog random access memory (ARAM) delay elements configured to delay signals received from the receive elements and provide the delayed signals on an output of the receive beamformer as a beamformed RF output. The beamformed RF output is suitable for use in forming an image of the region of interest.

US Patent:

6972707, Dec 6, 2005

Filed:

Jul 12, 2004

Appl. No.:

10/889282

Inventors:

Michael P. Anthony - Andover MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H03M001/12

US Classification:

341172, 341162

Abstract:

A pipelined analog-to-digital converter in which signal value samples are represented differentially by pairs of charges and which uses charge-coupled-devices (CCDs) for delay and arithmetic operations on the charges is presented. In the pipeline, each successive stage resolves an equal or smaller charge difference. After a certain number of pipeline stages, the common-mode component of the signal-charge pair is reduced. The pipeline stages following this common-mode-charge reduction stage have a reduced charge capacity and size, allowing more sensitive charge comparison. The result is improved A/D converter resolution and reduced power consumption.

US Patent:

7003068, Feb 21, 2006

Filed:

Jun 21, 2004

Appl. No.:

10/872820

Inventors:

Lawrence J. Kushner - Andover MA, US
Michael P. Anthony - Andover MA, US
Edward Kohler - Waltham MA, US

Assignee:

Kenet, Inc. - Reading MA

International Classification:

G11C 19/28
H03K 23/46

US Classification:

377 57, 377 62, 377 63

Abstract:

A circuit for adding or subtracting an amount of charge from a charge sample, such as in a Charge Coupled Device (CCD), by portioning and pipelining the processing stages, to avoid introducing a memory effect. The operation, such as subtraction, is split into multiple stages, with each stage responsible for removing only a portion of the total amount of charge that is desired to be removed. The subtraction pipeline stages operate together to remove the total desired charge amount. In one embodiment each successive subtraction stage removes a corresponding lesser amount of charge. As a result, greater accuracy in the amount of charge removed is achieved as well operation at higher frequencies than previous charge subtraction approaches.

US Patent:

7015854, Mar 21, 2006

Filed:

Jul 12, 2004

Appl. No.:

10/889281

Inventors:

Michael P. Anthony - Andover MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H03M 1/12

US Classification:

341172, 341162

Abstract:

A new architecture is provided in which a master A/D converter of limited precision controls the adjustment-charge steering of a set of similar slave A/D converter pipelines. This architecture relieves the layout constraints imposed by prior architectures and also reduces power consumption of the device. By spatially interleaving the slave pipelines in an array, the new architecture also improves accuracy.

US Patent:

7079067, Jul 18, 2006

Filed:

Jul 6, 2005

Appl. No.:

11/175897

Inventors:

Michael P. Anthony - Andover MA, US
Lawrence J. Kushner - Andover MA, US

Assignee:

Kenet, Inc. - Woburn MA

International Classification:

H03M 1/78

US Classification:

341154, 365154

Abstract:

An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.

US Patent:

7106230, Sep 12, 2006

Filed:

Jun 17, 2004

Appl. No.:

10/870330

Inventors:

Lawrence J. Kushner - Andover MA, US
Michael P. Anthony - Andover MA, US

Assignee:

Kenet, Inc. - Woburn MA

International Classification:

H03M 1/10

US Classification:

341120, 341118

Abstract:

A technique for dynamically calibrating a successive approximation charge to digital converter by toggling at least some portion of the converter between two predetermined states, with the design goal of balancing the voltage and/or charge that is output in the two states. The two states are chosen such that they are expected to generate the same output voltage when the converter is in normal operation mode. If there is an imbalance, switching between the two calibration states invariably generates a square wave signal that toggles between two distinct values. A synchronous demodulator having a bandwidth centered at the toggle frequency can then be used to accurately detect an amount of error, which is then feedback to generate correction signals. The detected value of the error signal can in turn can be further integrated over time, to provide a correction value. If there are undesirable static offsets introduced by the synchronous demodulator or by the signal and/or charge levels output by the two differential halves of the converter, a properly timed latch can be used to further stabilize the error signal.