Michael C Beck

US Patent:

7332428, Feb 19, 2008

Filed:

Feb 28, 2005

Appl. No.:

11/067877

Inventors:

Michael Beck - Poughkeepsie NY, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 23/48

US Classification:

438637, 257751, 257622, 257E23141, 438639, 438625

Abstract:

In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric layer. A liner is formed over the dual damascene structure. The liner is selectively removed from above the upper surface of the conductive region to expose the upper surface of the conductive region. After the selectively removing process, at least a portion of the liner remains over the lower surface of the trench and the sidewalls of the trench and the via hole. A wet etch can then be performed to etch a recess in the conductive region. A conductive material is then formed within the damascene structure. This conductive material physically contacts the conductive region and is separated from the dielectric layer by the remaining portion of the liner.

US Patent:

7452804, Nov 18, 2008

Filed:

Aug 16, 2005

Appl. No.:

11/204982

Inventors:

Michael Beck - Poughkeepsie NY, US
Bee Kim Hong - Beacon NY, US
Armin Tilke - Beacon NY, US
Hermann Wendt - Poughkeepsie NY, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 21/00

US Classification:

438627, 438926, 257E21585

Abstract:

In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.

US Patent:

7651942, Jan 26, 2010

Filed:

Aug 15, 2005

Appl. No.:

11/203883

Inventors:

Frank Huebinger - Poughkeepsie NY, US
Michael Beck - Poughkeepsie NY, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 21/4763

US Classification:

438639, 438638, 438702, 257E21579, 257E2158

Abstract:

A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.

US Patent:

7691736, Apr 6, 2010

Filed:

Feb 10, 2006

Appl. No.:

11/352047

Inventors:

Michael Beck - Poughkeepsie NY, US
John A. Fitzsimmons - Poughkeepsie NY, US
Karl Hornik - Laaber, DE
Darryl Restaino - Modena NY, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 21/4763

US Classification:

438622, 438627, 438628, 438629, 438654, 438687, 438683, 257760, 257E21257, 257E21261, 257E21271, 257E21292

Abstract:

Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (≦2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.

US Patent:

8093150, Jan 10, 2012

Filed:

Sep 19, 2006

Appl. No.:

11/523207

Inventors:

Michael Beck - Poughkeepsie NY, US
Erdem Kaltalioglu - Newburgh NY, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 21/4763

US Classification:

438638, 438706, 257E21571

Abstract:

Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern.

US Patent:

20060205204, Sep 14, 2006

Filed:

Mar 14, 2005

Appl. No.:

11/079843

Inventors:

Michael Beck - Poughkeepsie NY, US

International Classification:

H01L 21/4763

US Classification:

438628000, 438638000

Abstract:

A method for forming metallization is particularly useful for semiconductor devices having a critical dimension of less than 160 nm. A semiconductor wafer includes an insulating layer having an upper surface. First and second trenches are formed in the insulating layer. In one embodiment, the first trench is separated from the second trench by less than 160 nm. A barrier material is formed to line the trenches and also overlies the insulating layer between the trenches. A conductive material (e.g., copper) is formed within the trenches. The conductive material is then recessed within the trenches and a metal cap layer is selectively formed over the conductive material in the trenches. The barrier material overlying the insulating layer between the first trench and the second trench is then removed. This removal will further remove any residual portions of the metal cap layer from between the first trench and the second trench.