Michael D Boyer

US Patent:

20230130969, Apr 27, 2023

Filed:

Oct 27, 2021

Appl. No.:

17/512662

Inventors:

- Santa Clara CA, US
Vaibhav Ramakrishnan Ramachandran - Cupertino CA, US
Michael W. Boyer - Redmond WA, US

International Classification:

G11C 7/08
G11C 8/12
G11C 8/14
G11C 8/16

Abstract:

A memory includes two or more portions of memory circuitry and two or more processor in memory (PIM) functional blocks, each PIM functional block associated with a respective portion of the memory circuitry. In operation, at least one other PIM functional block other than a particular PIM functional block copies data from a source location accessible to the other PIM functional block. The other PIM functional block then provides the data to the particular PIM functional block. The particular acquires and stores the data in a destination location accessible to the particular PIM functional block. The particular PIM functional block next performs one or more PIM operations using the data.

US Patent:

20190163632, May 30, 2019

Filed:

Nov 29, 2017

Appl. No.:

15/825880

Inventors:

- Santa Clara CA, US
Michael W. BOYER - Bellevue WA, US
Yasuko ECKERT - Bellevue WA, US
Gabriel H. LOH - Bellevue WA, US

International Classification:

G06F 12/0817
G06F 12/0831
G06F 12/128
G06F 12/0811

Abstract:

A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.

US Patent:

20180074958, Mar 15, 2018

Filed:

Sep 14, 2016

Appl. No.:

15/264804

Inventors:

- Sunnyvale CA, US
Michael Boyer - Bellevue WA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 12/0811

Abstract:

A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.

US Patent:

20170293560, Oct 12, 2017

Filed:

Sep 19, 2016

Appl. No.:

15/268953

Inventors:

- Sunnyvale CA, US
Nuwan Jayasena - Sunnyvale CA, US
Reena Panda - Austin TX, US
Onur Kayiran - Sunnyvale CA, US
Michael W. Boyer - Bellevue WA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 12/0862

Abstract:

A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is to be prefetched.

US Patent:

20160335064, Nov 17, 2016

Filed:

May 12, 2015

Appl. No.:

14/709915

Inventors:

- Sunnyvale CA, US
Sudhanva Gurumurthi - Boxborough MA, US
Michael W. Boyer - Bellevue WA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9/45
G06F 9/44

Abstract:

A method, a system, and a non-transitory computer readable medium for generating application code to be executed on an active storage device are presented. The parts of an application that can be executed on the active storage device are determined. The parts of the application that will not be executed on the active storage device are converted into code to be executed on a host device. The parts of the application that will be executed on the active storage device are converted into code of an instruction set architecture of a processor in the active storage device.