Michael L Calhoun

US Patent:

7711887, May 4, 2010

Filed:

Apr 30, 2007

Appl. No.:

11/796790

Inventors:

Lidia Warnes - Roseville CA, US
Michael Bozich Calhoun - Roseville CA, US
Dennis Carr - Roseville CA, US
Teddy Lee - Roseville CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/36

US Classification:

710315, 710310

Abstract:

A translator of an apparatus in an example employs a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) to write to a plurality of parallel protocol memory module channels that comprises a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).

US Patent:

7729126, Jun 1, 2010

Filed:

Jul 31, 2007

Appl. No.:

11/882263

Inventors:

Michael Bozich Calhoun - Roseville CA, US
Dennis Carr - Roseville CA, US
Teddy Lee - Roseville CA, US
Lidia Warnes - Roseville CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H05K 7/18

US Classification:

361801, 361798

Abstract:

A modular DIMM carrier and riser slot device includes a slot section having a slot configured to hold a plurality of memory device planars, a first latch disposed at a first end of the slot section and pivotably connected to the slot section and capable of securing a first end of the memory device planars; a second latch disposed at a second end of the slot section and pivotably connected to the slot section and capable of securing a second end of a first memory device planar, and a third latch pivotably connected to the slot section and disposed intermediate between the first and the second latches, the third latch capable of securing a second end of a second memory device planar. The slot section has an auxiliary slot section defined as an section between the second latch and the third latch. The auxiliary slot section includes a notch for receiving the third latch when the third latch is in a disengaged position, a retention notch that restrains movement of the third latch when the third latch is in an engaged position, and a power and signaling section that includes power and signaling connections usable by one or more of the memory device planars.

US Patent:

7739441, Jun 15, 2010

Filed:

Apr 30, 2007

Appl. No.:

11/796748

Inventors:

Teddy Lee - Roseville CA, US
Michael Bozich Calhoun - Roseville CA, US
Dennis Carr - Roseville CA, US
Lidia Warnes - Roseville CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/36

US Classification:

710315, 710308, 710306

Abstract:

A translator of an apparatus in an example communicatively interconnects a serial protocol bus that follows a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) and three or more parallel protocol memory module channels that comprise a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).

US Patent:

7741867, Jun 22, 2010

Filed:

Oct 30, 2008

Appl. No.:

12/262051

Inventors:

Dennis Carr - Roseville CA, US
Lidia Warnes - Roseville CA, US
Dan Vu - Elk Grove CA, US
Teddy Lee - Roseville CA, US
Michael Bozich Calhoun - Roseville CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H03K 19/003

US Classification:

326 30, 326 27

Abstract:

Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals.

US Patent:

8018753, Sep 13, 2011

Filed:

Oct 30, 2008

Appl. No.:

12/262038

Inventors:

Dennis Carr - Roseville CA, US
Michael Bozich Calhoun - Roseville CA, US
Teddy Lee - Roseville CA, US
Lidia Warnes - Roseville CA, US
Dan Vu - Elk Grove CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 5/06

US Classification:

365 63, 365226

Abstract:

Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second plurality of pins coupled to power rails on the memory module that enable monitoring of the power rails from external to the memory module.

US Patent:

8225031, Jul 17, 2012

Filed:

Oct 30, 2008

Appl. No.:

12/262063

Inventors:

Teddy Lee - Roseville CA, US
Lidia Warnes - Roseville CA, US
Dan Vu - Elk Grove CA, US
Dennis Carr - Roseville CA, US
Michael Bozich Calhoun - Roseville CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/30

US Classification:

711105, 365 51, 365211, 36523313

Abstract:

A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions.

US Patent:

8275956, Sep 25, 2012

Filed:

Jun 24, 2011

Appl. No.:

13/168455

Inventors:

Lidia Warnes - Roseville CA, US
Teddy Lee - Roseville CA, US
Dennis Carr - Roseville CA, US
Michael Bozich Calhoun - Roseville CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711154, 711167, 711E12001

Abstract:

A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).

US Patent:

8539145, Sep 17, 2013

Filed:

Jul 28, 2009

Appl. No.:

12/510822

Inventors:

Lidia Warnes - Roseville CA, US
Dennis Carr - Roseville CA, US
Michael B. Calhoun - Roseville CA, US
Aaron R. Mandle - Roseville CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/00

US Classification:

711105, 36518905, 36523006, 711115

Abstract:

A computer-implemented method for increasing a number of ranks per channel. The channel comprises at least one buffered dual in-line memory module (DIMM). The at least one buffered DIMM comprises a conventional number of ranks and a conventional number of pins. The method includes receiving a memory access request at a memory controller, wherein the memory controller comprises a conventional number of pins. The method also includes encoding a plurality of chip-select (CS) signals at the memory controller, wherein the plurality of CS signals are based on the memory access request, such that the number of ranks per channel increases compared to a conventional number of ranks per channel while not requiring an increase in the number of pins in the memory controller compared to the conventional number of pins of the memory controller.