Michael F Carroll

US Patent:

6356496, Mar 12, 2002

Filed:

Jul 7, 2000

Appl. No.:

09/612052

Inventors:

Michael Scott Carroll - Orlando FL
Frank Yauchee Hui - Orlando FL
Tony G. Ivanov - Orlando FL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G11C 700

US Classification:

3652257, 36518503, 257209

Abstract:

A resistor fuse for use in a semiconductor device having an operating voltage. In one embodiment, the resistor fuse includes a silicon layer located over a semiconductor wafer and a metal silicide layer located over the silicon layer. The resistor fuse has a predetermined current threshold and is configured to open if a current through the resistor fuse at the operating voltage exceeds the current threshold.

US Patent:

6359317, Mar 19, 2002

Filed:

Dec 28, 1998

Appl. No.:

09/222587

Inventors:

Michael S. Carroll - Orlando FL
Yih-Feng Chyan - Orlando FL
Samir Chaudhry - Orlando FL
Tony G. Ivanov - Orlando FL
Robert W. Dail - Orlando FL
Alan S. Chen - Windermere FL

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 2976

US Classification:

257370, 257378

Abstract:

A bipolar vertical PNP transistor compatible with CMOS processing and useful in a complementary BiMOS structure is characterized in that it is devoid of an epitaxial layer and employs a high-energy implanted phosphorus layer to provide N-type substrate isolation.

US Patent:

6844236, Jan 18, 2005

Filed:

Jul 23, 2001

Appl. No.:

09/911364

Inventors:

Tony G. Ivanov - Orlando FL, US
Michael S. Carroll - Orlando FL, US
Ranbir Singh - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2176

US Classification:

438406, 438454, 438430

Abstract:

A method for electromagnetically shielding circuits which combine to form an integrated circuit device provides isolated silicon islands surrounded laterally and subjacently by conductive material. The isolated silicon islands may be covered individually or as a group by a conductive cover. The integrated circuit may include at least one silicon island including an analog circuit and at least one silicon island including a digital circuit, the analog and digital circuits electromagnetically shielded from one another. The method for forming the structure includes providing a first semiconductor substrate and hydrophilically bonding a substructure to the first semiconductor substrate. The substructure includes the isolated silicon islands surrounded by the conductive material. The substructure may be formed on a second semiconductor substrate by implanting an impurity region into an upper portion of the second semiconductor substrate. After bonding, the substructure may be separated from the remainder of the second substrate by propagating a crack along the boundary of the impurity region which separates the substructure from the remainder of the second semiconductor substrate.

US Patent:

6847077, Jan 25, 2005

Filed:

Jun 25, 2002

Appl. No.:

10/180910

Inventors:

Sylvia W. Thomas - Orlando FL, US
Michael Jay Parrish - St. Cloud FL, US
Tony G. Ivanov - Orlando FL, US
Edward Belden Harris - Orlando FL, US
Richard William Gregor - Winter Park FL, US
Michael Scott Carroll - Orlando FL, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 27108

US Classification:

257301, 257303, 257306

Abstract:

A semiconductor device having a capacitor integrated in a damascene structure. In one embodiment, the capacitor is formed entirely within a metallization layer of a damascene structure, having therein a semiconductor device component. Preferably, the capacitor is formed within a trench, having been etched in the dielectric material of the metal layer and the capacitor includes a first capacitor electrode formed within the recess in electrical contact with the device component of the metallization layer. An insulator may be formed over the first capacitor electrode, with a second capacitor electrode formed over the insulator. These elements are preferably conformally deposited within the trench, thereby forming a recess, a portion of which extends within the trench. A subsequently fabricated device component may then be placed in electrical contact with the second capacitor electrode.

US Patent:

6940151, Sep 6, 2005

Filed:

Sep 30, 2002

Appl. No.:

10/261463

Inventors:

Michael Scott Carroll - Orlando FL, US
Yi Ma - Santa Clara CA, US
Minesh Amrat Patel - Orlando FL, US
Peyman Sana - Orlando FL, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L031/0392

US Classification:

257649, 257636, 257630, 257640

Abstract:

A low-thermal budget, silicon-rich silicon nitride film may include a concentration of hydrogen in Si—H bonds being at least 1. 5 times as great as a concentration of hydrogen in N—H bonds. The silicon nitride film suppresses boron diffusion in boron-doped devices when such devices are processed using high-temperature processing operations that conventionally urge boron diffusion. The low-thermal budget, silicon-rich silicon nitride film may be used to form spacers in CMOS devices, it may be used as part of a dielectric stack to prevent shorting in tightly packed SRAM arrays, and it may be used in BiCMOS processing to form a base nitride layer and/or nitride spacers isolating the base from the emitter. Furthermore the low-thermal budget, silicon-rich silicon nitride film may remain covering the CMOS structure while bipolar devices are being formed, as it suppresses the boron diffusion that results in boron penetration and boron-doped poly depletion.

US Patent:

7095094, Aug 22, 2006

Filed:

Sep 29, 2004

Appl. No.:

10/953894

Inventors:

Daniel Charles Kerr - Orlando FL, US
Michael Scott Carroll - Orlando FL, US
Amal Ma Hamad - Frisco TX, US
Thiet The Lai - Orlando FL, US
Roger W. Key - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 27/102

US Classification:

257526, 257499, 257506, 257E27015

Abstract:

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.

US Patent:

7449388, Nov 11, 2008

Filed:

Jul 18, 2006

Appl. No.:

11/458270

Inventors:

Daniel Charles Kerr - Orlando FL, US
Michael Scott Carroll - Orlando FL, US
Amal Ma Hamad - Frisco TX, US
Thiet The Lai - Orlando FL, US
Roger W. Key - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 21/331

US Classification:

438309

Abstract:

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.

US Patent:

7713811, May 11, 2010

Filed:

Oct 1, 2008

Appl. No.:

12/243137

Inventors:

Daniel Charles Kerr - Orlando FL, US
Michael Scott Carroll - Orlando FL, US
Amal Ma Hamad - Frisco TX, US
Thiet The Lai - Orlando FL, US
Roger W. Key - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 21/8249

US Classification:

438235, 257E33016

Abstract:

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.

Address:

2457 Collins Ave APT 1504, Miami Beach, FL 33140

VIN:

1J4FA24177L213729

Make:

JEEP

Model:

WRANGLER

Year:

2007