Michael Chin Chen

US Patent:

6757882, Jun 29, 2004

Filed:

Apr 24, 2002

Appl. No.:

10/132587

Inventors:

Michael Y. Chen - Lake Oswego OR 97035
Michael C. Brouhard - Lake Oswego OR 97034
John Wilson - Wokingham R940 4TZ, GB

International Classification:

G06F 1750

US Classification:

716 12, 716 1, 716 5, 716 3

Abstract:

An IP package is formed with at least one of one or more components of an IP block and one or more pointers to locations where the components can be retrieved, and machine readable connectivity descriptions describing how the IP block is to be connected to include the IP block in an integrated circuit. In one embodiment, the connectivity descriptions include physical pin, implemented bus signals, handling of unimplemented bus signals, and mapping descriptions. In various embodiments, the IP package may further include one or more selected ones of customizable attribute, UI choice elements, embedded and/or diagnostic software, test vectors, supplemental generators and verification environment configuration requirement descriptions. The self-describing packaging advantageously enables an EDA tool suite to offer and facilitate selection of the IP block for a SOC design.

US Patent:

7447942, Nov 4, 2008

Filed:

Jul 19, 2005

Appl. No.:

11/184224

Inventors:

Michael Chen - Kirkland WA, US
Mark S. Larsen - Redmond WA, US
James A. Stulz - Bellevue WA, US
Gregory Hogdal - Sammamish WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 11/00

US Classification:

714 38, 717129, 717124

Abstract:

A technique to implement software debugging capability using breakpoints includes creating breakpoints, storing them in a watchlist, and paging out a virtual address (VA) to physical address (PA) page entry in a translation look-aside buffer (TLB). When software under test is run at full speed, memory is accessed via the TLB VA to PA page translations. When a translation is missing, an exception is generated. Handling the exception includes determining if the page missing from the TLB matches a breakpoint address in the watchlist. The address and operation type are compared to the watchlist. If the operation matches the address and not the specified data, then the software under test is single stepped, the TLB page is removed and the software under test continues to execute. If the breakpoint and data type matches, then a debugger is notified and debugger action to service the breakpoint occurs.

US Patent:

20030005396, Jan 2, 2003

Filed:

Apr 24, 2002

Appl. No.:

10/132040

Inventors:

Michael Chen - Lake Oswego OR, US
Michael Brouhard - Lake Oswego OR, US
John Wilson - Wokingham, GB

International Classification:

G06F017/50

US Classification:

716/005000

Abstract:

An EDA tool suite is equipped with the ability to responsively invoke a chain of one or more generators corresponding to one or more phases of a design/verification process to process design information of IP blocks forming a SOC design to transform the design information, as a result of each invocation, from one state to another state. In one embodiment, the phases may be one or more of a design generation phase, a simulation hardware logic generation phase, an embedded/diagnostic software generation phase, and a verification environment configuration script generation phase.

US Patent:

20030009730, Jan 9, 2003

Filed:

Apr 24, 2002

Appl. No.:

10/132020

Inventors:

Michael Chen - Lake Oswego OR, US
Michael Brouhard - Lake Oswego OR, US
John Wilson - Berkshire, GB

International Classification:

G06F017/50

US Classification:

716/005000

Abstract:

Enhanced Platform Based SOC Design Including Extended Peripheral Selection and Automated IP Customization Facilitation An EDA tool suite is provided to facilitate SOC design in a platform based manner, by first facilitating the selection of a compute engine, then supporting peripheral devices layered upon the compute engine in at least a single peripheral layer. In various embodiments, the EDA tool suite includes pre-processing functions to identify connectivity of an IP component, and automatic creation of a user interface to facilitate provision of customization inputs. The EDA tool suite further includes bus bridges bridging a plurality of bus architecture pairs, and component selection facilities that automatically provides an expanded list of components for selection, including components connectable to a selected compute engine by way of a pre-provided bus bridge, responsive to the selection of the compute engine.

US Patent:

20100077385, Mar 25, 2010

Filed:

Sep 23, 2008

Appl. No.:

12/236174

Inventors:

Javier Nisim Flores Assad - Bothell WA, US
Michael Hung-Hsiang Chen - Bellevue WA, US
John Robert Eldridge - Bellevue WA, US
Gregory Hogdal - Sammamish WA, US

Assignee:

MICROSOFT CORPORATION - Redmond WA

International Classification:

G06F 9/44

US Classification:

717129

Abstract:

Filtering exceptions on a target computing device to selectively interrupt a host computing device based on rules. The rules represent user-defined scenarios, and each rule includes one or more criteria and a break decision. Upon detecting an exception on the target computing device, the target computing device evaluates the rules based on the criteria and information about the exception without notifying the host computing device. For example, a score is calculated for each rule, and the rule with the highest score is selected. The break decision associated with the selected rule is applied. For example, the break decision indicates that the exception is of interest and the host computing device should be notified, or that the exception does not match a scenario of interest and execution should continue without a break.

US Patent:

20140005469, Jan 2, 2014

Filed:

Jun 21, 2013

Appl. No.:

13/923874

Inventors:

Adam Xiao - Fallston MD, US
Kelsey Humphries - Boise ID, US
Shida Li - West Chester PA, US
Michael Chen - Portland OR, US
Amanda Ojeda - Easton PA, US
Logan Howard - Surfside Beach SC, US

International Classification:

A61F 2/00

US Classification:

600 30, 29592

Abstract:

An urogynecologic implant has a curved body that disperses force and reduces the ability of the urethra to expand into the pelvic floor under impulses of abdominal pressure in order to inhibit, reduce or prevent stress urinary incontinence.

US Patent:

20170329997, Nov 16, 2017

Filed:

May 11, 2016

Appl. No.:

15/152427

Inventors:

- Wilsonville OR, US
Eugene Kishinevsky - Portland OR, US
Michael Chen - Happy Valley OR, US

International Classification:

G06F 21/71
G06F 21/76

Abstract:

This application discloses an electronic system including active circuitry configured to be selectively enabled for authorized number of times. The electronic system also includes security circuitry to detect an enablement event associated with the electronic system. The enablement event can correspond to reception of a reset signal associated with the electronic system, a lapse of a predetermined time period, or the like. In response to the detection of the enablement event, the security circuitry can determine a number of times the security circuitry has previously enabled the active circuitry. The security circuitry can generate the enablement signals capable of enabling the active circuitry when the determined number of times the security circuitry has previously enabled the active circuitry is fewer than the authorized number of times.

US Patent:

20170132434, May 11, 2017

Filed:

Nov 24, 2015

Appl. No.:

14/951176

Inventors:

- Wilsonville OR, US
Joseph P. Skudlarek - Lake Oswego OR, US
Mario Larouche - Lake Oswego OR, US
Michael Chen - Happy Valley OR, US

International Classification:

G06F 21/75
G06F 21/76

Abstract:

This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can extract bits from the outputs at various inspection locations and utilize the extracted bits to generate an identifier for the physical unclonable function device. An inspection configuration tool can identify the inspection locations and configure the physical unclonable function device with the inspection locations. The inspection configuration tool can sample the physical unclonable function circuitry to identify a plurality of multi-bit outputs, select bit locations in the multi-bit outputs as inspection locations based on bit value stability for the bit locations, and configure the identifier generation circuitry in physical unclonable function device with the inspection locations.