Michael Douglas Chisholm

US Patent:

6495907, Dec 17, 2002

Filed:

Jun 7, 1995

Appl. No.:

08/473404

Inventors:

Manoj Kumar Jain - Plano TX
Michael Francis Chisholm - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23495

US Classification:

257667, 257669

Abstract:

A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by e. g. , chemical mechanic polishing or etchback, may be reduced or avoided entirely.

US Patent:

6586839, Jul 1, 2003

Filed:

Aug 23, 2001

Appl. No.:

09/938261

Inventors:

Michael F. Chisholm - Garland TX
Darvin R. Edwards - Garland TX
Gregory B. Hotchkiss - Richardson TX
Reynaldo Rincon - Richardson TX
Viswanathan Sundararaman - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348

US Classification:

257773, 257786

Abstract:

A conductive via pattern ( ) between the uppermost metal interconnect layer (M ) and next underlying metal interconnect layer (M ) in the bond pad areas strengthens the interlevel dielectric (ILD ) between metal layers (M and M ). The conductive via layer ( ) may, for example, comprise parallel rails ( ) or a grid of cross-hatch rails ( ). By spreading the stress concentration laterally, the conductive via layer ( ) inhibits micro-cracking from stress applied to the bond pad ( ).

US Patent:

6653717, Nov 25, 2003

Filed:

Dec 17, 2002

Appl. No.:

10/320968

Inventors:

Manoj Kumar Jain - Plano TX
Michael Francis Chisholm - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2978

US Classification:

257632, 257691, 257752

Abstract:

A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critcal width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e. g. , chemical mechanic polishing or etchback, may be reduced or avoided entirely.

US Patent:

55955274, Jan 21, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/474605

Inventors:

Andrew T. Appel - Dallas TX
Michael F. Chisholm - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B24B 100

US Classification:

451 28

Abstract:

A pad conditioning method and apparatus for chemical-mechanical polishing. A polishing pad (114) is attached to a platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. During wafer polishing particles build up on the polishing pad (114) reducing its effectiveness. Either during or in between wafer polishing (or both), conditioning head (122) is applied to pad (114) to remove the particles from pad (114) into the slurry (120). Conditioning head (122) comprises a semiconductor substrate (126) that is patterned and etched to fore a plurality of geometries (128) having a feature size on the order of polishing pad (114) cell size.

US Patent:

60777834, Jun 20, 2000

Filed:

Jun 30, 1998

Appl. No.:

9/109335

Inventors:

Derryl D. J. Allman - Colorado Springs CO
David W. Daniel - Divide CO
Michael F. Chisholm - Garland TX

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21302

US Classification:

438691

Abstract:

A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.

US Patent:

54628822, Oct 31, 1995

Filed:

Oct 31, 1994

Appl. No.:

8/332276

Inventors:

Michael F. Chisholm - Plano TX
David I. Forehand - Wylie TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 3118
H01L 21324
H01L 21326

US Classification:

437 5

Abstract:

Only the areas of the CdTe/HgCdTe interface of a FPA detector circuit which is coupled by an epoxy to a silicon-based integrated circuit that require interdiffusing are heated to a sufficiently high temperature or have photons of light impinging thereon for a sufficient time to cause interdiffusion of the two layers by the travel of tellurium into the HgCdTe and the travel of mercury into the CdTe. The vast majority of the wafer is masked with an aluminum thin film to greatly reduce heat gain or photon transmission. An advantage of the process in accordance with the present invention is that only a very small fraction of the HgCdTe/epoxy/silicon-based integrated circuit wafer receives incoming energy during interdiffusion whereby problems caused by the differences in coefficient of thermal expansion between silicon and HgCdTe at the epoxy interface are minimized.

US Patent:

57559791, May 26, 1998

Filed:

Sep 24, 1996

Appl. No.:

8/719106

Inventors:

Andrew T. Appel - Dallas TX
Michael Francis Chisholm - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G03F 700

US Classification:

216 41

Abstract:

A pad conditioning method and apparatus for chemical-mechanical polishing. A polishing pad (114) is attached to a platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. During wafer polishing particles build up on the polishing pad (114) reducing its effectiveness. Either during or in between wafer polishing (or both), conditioning head (122) is applied to pad (114) to remove the particles from pad (114) into the slurry (120). Conditioning head (122) comprises a semiconductor substrate (126) that is patterned and etched to form a plurality of geometries (128) having a feature size on the order of polishing pad (114) cell size.

US Patent:

56863560, Nov 11, 1997

Filed:

Sep 30, 1994

Appl. No.:

8/315529

Inventors:

Manoj Kumar Jain - Plano TX
Michael Francis Chisholm - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144

US Classification:

437195

Abstract:

A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e. g. , chemical mechanic polishing or etchback, may be reduced or avoided entirely.