Michael R Clinton

US Patent:

7512030, Mar 31, 2009

Filed:

Aug 29, 2006

Appl. No.:

11/511800

Inventors:

Theodore Warren Houston - Richardson TX, US
Michael Patrick Clinton - Allen TX, US
Bryan David Sheffield - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 5/14

US Classification:

365226

Abstract:

The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode control circuitry coupled to the array and configured to alter a supply voltage level to the SRAM array based on a mode of operation. The circuitry also includes control inputs coupled to the mode control circuitry for selecting one of the low power write mode, the full active mode, and optionally a retention mode of operation. The mode control circuitry is configured to receive the control inputs to select one of the three modes of operation, and to alter one or more supply voltage levels to the array, for example, the Vss supply voltage using a Vss supply circuit and the Vdd supply voltage using a Vdd supply circuit, based on the selected mode of operation. The mode control circuitry may also comprise a bitline precharge circuit configured to alter a bitline precharge voltage.

US Patent:

7671663, Mar 2, 2010

Filed:

Dec 12, 2006

Appl. No.:

11/609678

Inventors:

Theodore W. Houston - Richardson TX, US
Michael P. Clinton - Allen TX, US
Robert L. Pitts - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 3/01

US Classification:

327534, 327544

Abstract:

The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.

US Patent:

7733686, Jun 8, 2010

Filed:

Dec 27, 2007

Appl. No.:

11/965604

Inventors:

Michael Patrick Clinton - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/00

US Classification:

365154, 365194

Abstract:

An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.

US Patent:

7864600, Jan 4, 2011

Filed:

Jun 19, 2008

Appl. No.:

12/142334

Inventors:

Hugh Mair - Fairview TX, US
Theodore W. Houston - Richardson TX, US
Michael Patrick Clinton - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/22

US Classification:

36518914, 36518915, 36518916, 365227

Abstract:

A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.

US Patent:

7936624, May 3, 2011

Filed:

Dec 27, 2007

Appl. No.:

11/965517

Inventors:

Michael Patrick Clinton - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/00

US Classification:

365203

Abstract:

A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished with a lower power supply, the second step completes the bitline precharge with the higher power supply. Since the higher power supply must ultimately supply the final bitline precharge voltage achieving a partial bitline precharge with a lower power supply will result in lower sram and system power.

US Patent:

7974144, Jul 5, 2011

Filed:

Dec 27, 2007

Appl. No.:

11/965639

Inventors:

Michael Patrick Clinton - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/00

US Classification:

365229, 365154, 365226, 365228

Abstract:

A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.

US Patent:

8248867, Aug 21, 2012

Filed:

Dec 1, 2010

Appl. No.:

12/957936

Inventors:

Hugh Mair - Fairview TX, US
Theodore W. Houston - Richardson TX, US
Michael Patrick Clinton - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/22

US Classification:

36518914, 365226, 365227, 365228, 365154

Abstract:

A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.

US Patent:

8266464, Sep 11, 2012

Filed:

Oct 22, 2007

Appl. No.:

11/876600

Inventors:

Michael P. Clinton - Allen TX, US
Uming U. Ko - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/32

US Classification:

713320, 713323, 713324

Abstract:

Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.