Michael J Colwell

US Patent:

6617621, Sep 9, 2003

Filed:

Jun 6, 2000

Appl. No.:

09/588802

Inventors:

Tushar R. Gheewala - Los Altos CA
Duane G. Breid - Lakeville MN
Deepak D. Sherlekar - Cupertino CA
Michael J. Colwell - Fremont CA

Assignee:

Virage Logic Corporation - Fremont CA

International Classification:

H01L 2710

US Classification:

257207, 257203, 257208

Abstract:

An metal programmable integrated circuit apparatus and method of manufacture and design using elevated metal layers for design-specific customization. The lower metal layer are used to form core cells and to provide power and clocking signals to the core cells. These core cell are customizable by the designer using only the upper metal layers. This new architecture allows faster turn-around time and fewer masks while keeping the time-to-market advantages of gate array structures.

US Patent:

6838713, Jan 4, 2005

Filed:

Jul 12, 1999

Appl. No.:

09/351767

Inventors:

Tushar R. Gheewala - Los Altos CA, US
Michael J. Colwell - Fremont CA, US
Henry H. Yang - San Jose CA, US
Duane G. Breid - Lakeville MN, US

Assignee:

Virage Logic Corporation - Fremont CA

International Classification:

H01L 3120
H01L 2900
H01L 27102
H01L 2994
H03K 190175

US Classification:

257211, 257 55, 257512, 257562, 257574, 257300, 257296, 257261, 257260, 376 63, 376114

Abstract:

A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.

US Patent:

7129562, Oct 31, 2006

Filed:

Oct 1, 2004

Appl. No.:

10/956689

Inventors:

Tushar R. Gheewala - Los Altos CA, US
Michael J. Colwell - Fremont CA, US
Henry H. Yang - San Jose CA, US
Duane G. Breid - Lakeville MN, US

Assignee:

Virage Logic Corporation - Fremont CA

International Classification:

H01L 29/80
H01L 29/76
H01L 29/00
H01L 23/98

US Classification:

257574, 257261, 257296, 257512, 257555, 257562, 257697

Abstract:

A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.

US Patent:

56442513, Jul 1, 1997

Filed:

Sep 26, 1995

Appl. No.:

8/533688

Inventors:

Michael Colwell - Livermore CA
Rochit Rajsuman - San Jose CA
Ray Abrishami - Los Altos CA
Zarir B. Sarkari - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 1900

US Classification:

326 16

Abstract:

An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.

US Patent:

57773548, Jul 7, 1998

Filed:

Apr 21, 1997

Appl. No.:

8/837570

Inventors:

Gary H. Cheung - Fremont CA
Elias Lozano - Sunnyvale CA
Trung Nguyen - San Jose CA
Michael J. Colwell - Livermore CA
Kevin Atkinson - Eden Prairie MN

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 27118

US Classification:

257202

Abstract:

An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.

US Patent:

57286124, Mar 17, 1998

Filed:

Jul 19, 1996

Appl. No.:

8/684022

Inventors:

Michael Colwell - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 218238

US Classification:

438200

Abstract:

A method and resulting structure is disclosed for extending or enlarging the effective volumes of one or more source, drain, and/or emitter regions of integrated circuit structures such as an SCR structure and/or an MOS structure designed to protect an integrated circuit structure from damage due to electrostatic discharge (ESD). The additional effective volume allows the SCR and/or MOS protection devices to handle additional energy from an electrostatic discharge applied, for example, to I/O contacts electrically connected to the SCR protection structure. The additional effective volume is obtained, without additional doping or masking steps, by forming individual deep doped regions or wells, beneath one or more heavily doped source, drain, and emitter regions, at the same time and to the same depth and doping concentration as conventional main P wells and/or N wells which are simultaneously formed in the substrate, whereby no additional masks and implanting steps are needed.

US Patent:

55523331, Sep 3, 1996

Filed:

Sep 16, 1994

Appl. No.:

8/307942

Inventors:

Gary H. Cheung - Fremont CA
Elias Lozano - Sunnyvale CA
Trung Nguyen - San Jose CA
Michael J. Colwell - Livermore CA
Kevin Atkinson - Eden Prairie MN

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2170

US Classification:

437 51

Abstract:

An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.

US Patent:

57604282, Jun 2, 1998

Filed:

Jan 25, 1996

Appl. No.:

8/596894

Inventors:

Michael J. Colwell - Fremont CA
Stephen P. Roddy - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2710

US Classification:

257206

Abstract:

A gate array masterslice having a minimal input/output slot and variable pad pitch architecture is disclosed. In the masterslice, many identical input/output slots ring the periphery of a semiconductor substrate and contain only the special devices necessary for input/output circuits. Each of the input/output slots include (i) a first region containing a plurality of tuning transistors of different sizes, (ii) a second region having one or more PMOS transistors, each of a size greater than any one of the plurality of tuning transistors, (iii) a third region having one or more NMOS transistors, each of a size greater than any one of the plurality of tuning transistors, and (iv) a fourth region containing one or more devices for providing electrostatic discharge protection. One to four PMOS transistors are provided in the second slot region and one to four NMOS transistors are provided in the third slot region. A plurality of bonding pads are provided, at least some of which are electrically connected to at least some of the input/output slots such that the plurality of bonding pads may have a variable bonding pad pitch.