Michael E Connell

US Patent:

6514795, Feb 4, 2003

Filed:

Oct 10, 2001

Appl. No.:

09/974192

Inventors:

Tongbi Jiang - Boise ID
Michael E. Connell - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2144

US Classification:

438113, 438460, 438464, 438109, 438114

Abstract:

A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto. In another aspect, the present invention is directed to a plurality of stacked semiconductor devices that comprise a first die, the first die having an upper surface, a second die positioned above the first die, the second die having a bottom surface, and an adhesive layer positioned between and coupled to each of the first die and the second die, the adhesive layer comprised of first and second surfaces, the first surface of the adhesive layer being coupled to the bottom surface of the second die thereby defining a first contact area, the second surface of the adhesive layer being coupled to the upper surface of the first die thereby defining a second contact area, the second contact area being less than the first contact area.

US Patent:

6762074, Jul 13, 2004

Filed:

Jan 21, 2003

Appl. No.:

10/348635

Inventors:

Nathan R. Draney - Boise ID
Michael E. Connell - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2144

US Classification:

438106, 438107, 438113, 438118

Abstract:

Methods and apparatuses for forming thin microelectronic dies. A method in accordance with one embodiment of the invention includes releasably attaching a microelectronic substrate to a support member with an attachment device. The microelectronic substrate can have a first surface, a second surface facing opposite from the first surface, and a first thickness between the first and second surfaces. The attachment device can have a releasable bond with the microelectronic substrate, wherein the bond has a bond strength that is reduced upon exposure to at least one energy. The support member can be at least partially transmissive to the at least one energy. The method can further include reducing a thickness of the microelectronic substrate and directing a quantity of the at least one energy through the support member to the attachment device to reduce the strength of the bond between the attachment device and the microelectronic substrate. At least a portion of the microelectronic substrate can then be separated from the support member. The support member can accordingly provide releasable support to the microelectronic substrate while the thickness of the microelectronic substrate is reduced.

US Patent:

6882036, Apr 19, 2005

Filed:

Apr 29, 2004

Appl. No.:

10/835369

Inventors:

Nathan R. Draney - Boise ID, US
Michael E. Connell - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L023/02

US Classification:

257678, 257749, 257753, 257783

Abstract:

Methods and apparatuses for forming thin microelectronic dies. A method in accordance with one embodiment of the invention includes releasably attaching a microelectronic substrate to a support member with an attachment device. The microelectronic substrate can have a first surface, a second surface facing opposite from the first surface, and a first thickness between the first and second surfaces. The attachment device can have a releasable bond with the microelectronic substrate, wherein the bond has a bond strength that is reduced upon exposure to at least one energy. The support member can be at least partially transmissive to the at least one energy. The method can further include reducing a thickness of the microelectronic substrate and directing a quantity of the at least one energy through the support member to the attachment device to reduce the strength of the bond between the attachment device and the microelectronic substrate. At least a portion of the microelectronic substrate can then be separated from the support member. The support member can accordingly provide releasable support to the microelectronic substrate while the thickness of the microelectronic substrate is reduced.

US Patent:

6894380, May 17, 2005

Filed:

Aug 28, 2002

Appl. No.:

10/230005

Inventors:

Tongbi Jiang - Boise ID, US
Michael E. Connell - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L023/02

US Classification:

257686

Abstract:

A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto. In another aspect, the present invention is directed to a plurality of stacked semiconductor devices that comprise a first die, the first die having an upper surface, a second die positioned above the first die, the second die having a bottom surface, and an adhesive layer positioned between and coupled to each of the first die and the second die, the adhesive layer comprised of first and second surfaces, the first surface of the adhesive layer being coupled to the bottom surface of the second die thereby defining a first contact area, the second surface of the adhesive layer being coupled to the upper surface of the first die thereby defining a second contact area, the second contact area being less than the first contact area.

US Patent:

6896760, May 24, 2005

Filed:

Jan 16, 2002

Appl. No.:

10/051890

Inventors:

Michael Connell - Boise ID, US
Tongbi Jiang - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B32B031/00

US Classification:

156249, 156268, 156299, 438109, 438114, 438464

Abstract:

Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of microelectronic components in a batch fashion. In one embodiment, an adhesive payer is applied on a rear surface of a wafer. A plurality of spaced-apart adhesive pads are defined within the adhesive layer. Each adhesive pad may cover less than the entire back surface area of the component to which it is attached. A mounting member (e. g. , dicing tape) may be attached to the adhesive layer and, in some embodiments, the adhesive layer may be treated so that the mounting member is less adherent to the adhesive pads than to other parts of the adhesive layer, easing removal of the adhesive pads with the microelectronic components.

US Patent:

6995442, Feb 7, 2006

Filed:

Jan 15, 2004

Appl. No.:

10/757589

Inventors:

Tongbi Jiang - Boise ID, US
Michael Connell - Boise ID, US
Jin Li - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 31/0232
H01L 21/00

US Classification:

257432, 257434, 257435, 257436, 438 48, 438 64, 438 65

Abstract:

The subject invention is directed to use of photoconductors as conductors of light to photo diodes in a CMOS chip, wherein said photoconductors are separated by at least one low refractive index material (i. e. air). The present invention offers advantages over previous CMOS imaging technology, including enhanced light transmission to photo diodes. The instant methods for producing a CMOS imaging device and CMOS imager system involve minimal power loss. Since no lens is required, the invention eliminates concerns about radius limitation and about damaging lenses during die attach, backgrind, and mount. The invention also provides little or no cross talk between photo diodes.

US Patent:

7001795, Feb 21, 2006

Filed:

Feb 27, 2003

Appl. No.:

10/373785

Inventors:

Tongbi Jiang - Boise ID, US
Michael Connell - Boise ID, US
Jin Li - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/00
H01L 31/0232

US Classification:

438 64, 438 48, 438 65, 438 69, 438 70, 257432, 257436

Abstract:

The subject invention is directed to use of photoconductors as conductors of light to photo diodes in a CMOS chip, wherein said photoconductors are separated by at least one low refractive index material (i. e. air). The present invention offers advantages over previous CMOS imaging technology, including enhanced light transmission to photo diodes. The instant methods for producing a CMOS imaging device and CMOS imager system involve minimal power loss. Since no lens is required, the invention eliminates concerns about radius limitation and about damaging lenses during die attach, backgrind, and mount. The invention also provides little or no cross talk between photo diodes.

US Patent:

7022418, Apr 4, 2006

Filed:

Sep 2, 2004

Appl. No.:

10/933794

Inventors:

Michael Connell - Boise ID, US
Tongbi Jiang - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/44
H01L 21/50

US Classification:

428621, 428 414, 428 423, 438109, 438114, 438464, 156249, 156268, 156299

Abstract:

Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of microelectronic components in a batch fashion. In one embodiment, an adhesive payer is applied on a rear surface of a wafer. A plurality of spaced-apart adhesive pads are defined within the adhesive layer. Each adhesive pad may cover less than the entire back surface area of the component to which it is attached. A mounting member (e. g. , dicing tape) may be attached to the adhesive layer and, in some embodiments, the adhesive layer may be treated so that the mounting member is less adherent to the adhesive pads than to other parts of the adhesive layer, easing removal of the adhesive pads with the microelectronic components.