Michael James Doerr

US Patent:

7415594, Aug 19, 2008

Filed:

Jun 24, 2003

Appl. No.:

10/602292

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/00

US Classification:

712 15, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

7937558, May 3, 2011

Filed:

Feb 8, 2008

Appl. No.:

12/028565

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/76
G06F 15/80

US Classification:

712 11, 712 15, 712 16, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

7987338, Jul 26, 2011

Filed:

May 17, 2010

Appl. No.:

12/781314

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/76
G06F 15/80

US Classification:

712 11, 712 15, 712 16, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

7987339, Jul 26, 2011

Filed:

Jun 30, 2010

Appl. No.:

12/827416

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/76
G06F 15/80

US Classification:

712 11, 712 15, 712 16, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

8112612, Feb 7, 2012

Filed:

May 17, 2010

Appl. No.:

12/781422

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/80

US Classification:

712 15, 712 14, 712 16, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

8151305, Apr 3, 2012

Filed:

Jul 3, 2008

Appl. No.:

12/167708

Inventors:

Michael B. Doerr - Dripping Springs TX, US
Peter J. Nysen - Sunnyvale CA, US
Colleen J. McGinn - Austin TX, US
Kevin A. Shelby - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

H04N 5/455
H04N 7/18
H04N 7/16

US Classification:

725 62, 725 80, 725 81, 725133, 725140

Abstract:

A digital television broadcast system with transmission and/or reception of digital television signals for improved mobile reception. The communication layers in the transmit and receive portions of the transmission system can be dynamically modified, e. g. , based on usage patterns or current channel characteristics. The transmission system also provides for cross layer control, whereby parameters in various of the communication layers are analyzed to determine appropriate updates to the system configuration.

US Patent:

8478964, Jul 2, 2013

Filed:

Dec 30, 2011

Appl. No.:

13/341252

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 9/00

US Classification:

712 15, 712225

Abstract:

A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

US Patent:

20120137119, May 31, 2012

Filed:

Oct 14, 2011

Appl. No.:

13/274138

Inventors:

Michael B. Doerr - Dripping Springs TX, US
Carl S. Dobbs - Austin TX, US
Michael B. Solka - Austin TX, US
Michael R. Trocino - Austin TX, US
David A. Gibson - Austin TX, US

International Classification:

G06F 9/00

US Classification:

713100

Abstract:

Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.