Michael Bauer Doerr

US Patent:

7415594, Aug 19, 2008

Filed:

Jun 24, 2003

Appl. No.:

10/602292

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/00

US Classification:

712 15, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

7937558, May 3, 2011

Filed:

Feb 8, 2008

Appl. No.:

12/028565

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/76
G06F 15/80

US Classification:

712 11, 712 15, 712 16, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

7987338, Jul 26, 2011

Filed:

May 17, 2010

Appl. No.:

12/781314

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/76
G06F 15/80

US Classification:

712 11, 712 15, 712 16, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

7987339, Jul 26, 2011

Filed:

Jun 30, 2010

Appl. No.:

12/827416

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/76
G06F 15/80

US Classification:

712 11, 712 15, 712 16, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

8112612, Feb 7, 2012

Filed:

May 17, 2010

Appl. No.:

12/781422

Inventors:

Michael B. Doerr - Dripping Springs TX, US
William H. Hallidy - Austin TX, US
David A. Gibson - Austin TX, US
Craig M. Chase - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

G06F 15/80

US Classification:

712 15, 712 14, 712 16, 712225

Abstract:

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

US Patent:

8151305, Apr 3, 2012

Filed:

Jul 3, 2008

Appl. No.:

12/167708

Inventors:

Michael B. Doerr - Dripping Springs TX, US
Peter J. Nysen - Sunnyvale CA, US
Colleen J. McGinn - Austin TX, US
Kevin A. Shelby - Austin TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

H04N 5/455
H04N 7/18
H04N 7/16

US Classification:

725 62, 725 80, 725 81, 725133, 725140

Abstract:

A digital television broadcast system with transmission and/or reception of digital television signals for improved mobile reception. The communication layers in the transmit and receive portions of the transmission system can be dynamically modified, e. g. , based on usage patterns or current channel characteristics. The transmission system also provides for cross layer control, whereby parameters in various of the communication layers are analyzed to determine appropriate updates to the system configuration.

US Patent:

8332896, Dec 11, 2012

Filed:

May 27, 2009

Appl. No.:

12/472892

Inventors:

Kevin A. Shelby - Austin TX, US
Peter J. Nysen - Sunnyvale CA, US
Michael B. Doerr - Dripping Springs TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

H04N 7/173
H03M 13/05
G06F 17/30

US Classification:

725 62, 714751

Abstract:

A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.

US Patent:

8347339, Jan 1, 2013

Filed:

May 30, 2009

Appl. No.:

12/475511

Inventors:

Kevin A. Shelby - Austin TX, US
Peter J. Nysen - Sunnyvale CA, US
Michael B. Doerr - Dripping Springs TX, US

Assignee:

Coherent Logix, Incorporated - Austin TX

International Classification:

H04N 7/16
H03H 7/30

US Classification:

725 62, 375231, 370465

Abstract:

A system and method for wirelessly transmitting audiovisual information. Training information may be stored in a memory. A plurality of packets may be generated, including the training information. The plurality of packets may also include audiovisual information. The plurality of packets may include first information identifying a first training pattern of a plurality of possible training patterns. The first training pattern may specify one or more locations of the training information in the plurality of packets. The first information may be usable by a receiver to determine the first training pattern of the plurality of possible training patterns. The plurality of packets may be transmitted in a wireless manner.