Michael Charles Elliott

US Patent:

6587065, Jul 1, 2003

Filed:

Apr 29, 2002

Appl. No.:

10/136895

Inventors:

Joseph Michael Hensley - Kernersville NC
Michael R. Elliott - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 114

US Classification:

341161, 341155

Abstract:

Current-control reference systems are provided in which stabliity is realized with sensors that shift clamp windows in response to a references current-control signal to thereby maintain feedback control in the reference under steady-state and transient operating conditions.

US Patent:

6812771, Nov 2, 2004

Filed:

Sep 16, 2003

Appl. No.:

10/664717

Inventors:

John Kevin Behel - Greensboro NC
Frank Murden - Greensboro NC
Michael Elliott - Summerfield NC
Joseph Michael Hensley - Kernersville NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06G 716

US Classification:

327359, 327356, 327563, 330254

Abstract:

Digitally-controlled, variable-gain mixers and amplifiers are provided which couple transconductance cells to receive respective tap signals from a fixed attenuator that receives a first input signal. A gain interpolator provides first and second control currents with amplitudes that correspond to a segment of a control word and a multiplexer responds to another control-word segment by routing the control currents to a selected pair of adjacent transconductance cells. In response, the transconductance cells provide amplifier current signals which can also be routed to a transistor switch that mixes them with a second input signal to generate a mixer output signal whose amplitude corresponds to the control word.

US Patent:

7405625, Jul 29, 2008

Filed:

Apr 25, 2007

Appl. No.:

11/789858

Inventors:

Joseph Michael Hensley - Lexington NC, US
Michael R. Elliott - Summerfield NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 3/45

US Classification:

330285, 330252, 330254, 330260, 341155, 341161

Abstract:

Control structures are provided to accurately maintain amplifier common-mode levels at the predetermined level of a common-mode reference voltage V. The disclosed control structures provide amplifier feedback along a first feedback path that is configured to provide high gain and low bandwidth to closely maintain amplifier common-mode level at the predetermined level of a common-mode reference voltage V. They also provide amplifier feedback along a second feedback path that is configured to provide wide bandwidth to substantially reduce perturbations of the common-mode level that would have otherwise been induced by input signal transients. In an important amplifier feature, these controls are obtained without use of structures (e. g. , capacitors and switching transistors) that use substantial current which reduces amplifier efficiency. Although the disclosed control structures may be used in a variety of systems, they are particularly suited for use in samplers and converter stages of pipelined analog-to-digital converters.

US Patent:

7652611, Jan 26, 2010

Filed:

May 20, 2008

Appl. No.:

12/123908

Inventors:

Michael Elliott - Summerfield NC, US
Frank Murden - Roan Mountain TN, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 1/38

US Classification:

341161, 341162, 341172

Abstract:

Embodiments of the present invention provide a pipeline ADC front-end sampling structure that provides a continuous time input signal to a flash comparator for sampling. By providing a continuous time input signal to the flash comparator, no delay is introduced from the need to transfer a DC charge representing the sampled input to the flash comparator. Matching sampling networks in the residual generator and the flash comparator are avoided due to the high bandwidth response requirements of the residual generator and the flash comparator when operating on high frequency input signals.

US Patent:

7719452, May 18, 2010

Filed:

Sep 23, 2008

Appl. No.:

12/284672

Inventors:

Scott Gregory Bardsley - Gibsonville NC, US
Bryan Scott Puckett - Stokesdale NC, US
Michael Ray Elliott - Summerfield NC, US
Ravi Kishore Kummaraguntla - Austin TX, US
Ahmed Mohamed Abdelatty Ali - Oak Ridge NC, US
Carroll Clifton Speir - Pleasant Garden NC, US
James Carroll Camp - Greensboro NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 1/20

US Classification:

341131, 341118, 341120, 341155, 341161, 341162

Abstract:

Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal. The final system digital code is realized by subtracting out the second portion with a back-end decoder that responds to the random digital code.

US Patent:

7870415, Jan 11, 2011

Filed:

Aug 24, 2007

Appl. No.:

11/895589

Inventors:

Ravi Kishore Kummaraguntla - High Point NC, US
Michael Elliott - Summerfield NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 1/04

US Classification:

713503, 341118, 341126

Abstract:

Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e. g. , temperature and clock rate), the shared use reduces processor costs.

US Patent:

7889004, Feb 15, 2011

Filed:

Sep 30, 2009

Appl. No.:

12/571038

Inventors:

Scott Gregory Bardsley - Gibsonville NC, US
Michael Elliott - Summerfield NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 3/45

US Classification:

330253, 330310

Abstract:

Operational amplifier embodiments are provided to enhance amplifier parameters such as bandwidth, stability, and headroom. In an amplifier embodiment, transistor followers are arranged with first and second differential pairs to facilitate selective positioning of first and second transfer function poles to enhance bandwidth and resistors and inductors are arranged to facilitate selective positioning of complex third transfer function poles to enhance phase margin. In another amplifier embodiment, the transistor followers are arranged to reduce headroom limitations to thereby enhance the voltage swing of output signals.

US Patent:

7974589, Jul 5, 2011

Filed:

Feb 13, 2008

Appl. No.:

12/069969

Inventors:

Brad Porcher Jeffries - Browns Summit NC, US
Michael R. Elliott - Summerfield NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04B 1/02

US Classification:

455 91, 455103, 4551271, 4551273, 4551275, 330252, 330253, 330255, 330310, 327108, 327335, 327423, 327588

Abstract:

Data transmitter embodiments are provided which are particularly useful as interface devices for accurate and reliable transmittal of data from high-speed data system devices such as analog-to-digital converters. Transmitter embodiments have been found to provide excellent fidelity of data transfer at high data rates (e. g. , 4 gigabits/second) while consuming only a portion of the power of many conventional transmitters and requiring only a portion of the layout area of these transmitters. Transmitter embodiments provide effective control of transmitter parameters such as matched impedances, data symmetry, common-mode level, data eye and current drain.