Michael L Elliott

US Patent:

6812771, Nov 2, 2004

Filed:

Sep 16, 2003

Appl. No.:

10/664717

Inventors:

John Kevin Behel - Greensboro NC
Frank Murden - Greensboro NC
Michael Elliott - Summerfield NC
Joseph Michael Hensley - Kernersville NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06G 716

US Classification:

327359, 327356, 327563, 330254

Abstract:

Digitally-controlled, variable-gain mixers and amplifiers are provided which couple transconductance cells to receive respective tap signals from a fixed attenuator that receives a first input signal. A gain interpolator provides first and second control currents with amplitudes that correspond to a segment of a control word and a multiplexer responds to another control-word segment by routing the control currents to a selected pair of adjacent transconductance cells. In response, the transconductance cells provide amplifier current signals which can also be routed to a transistor switch that mixes them with a second input signal to generate a mixer output signal whose amplitude corresponds to the control word.

US Patent:

7719452, May 18, 2010

Filed:

Sep 23, 2008

Appl. No.:

12/284672

Inventors:

Scott Gregory Bardsley - Gibsonville NC, US
Bryan Scott Puckett - Stokesdale NC, US
Michael Ray Elliott - Summerfield NC, US
Ravi Kishore Kummaraguntla - Austin TX, US
Ahmed Mohamed Abdelatty Ali - Oak Ridge NC, US
Carroll Clifton Speir - Pleasant Garden NC, US
James Carroll Camp - Greensboro NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 1/20

US Classification:

341131, 341118, 341120, 341155, 341161, 341162

Abstract:

Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal. The final system digital code is realized by subtracting out the second portion with a back-end decoder that responds to the random digital code.

US Patent:

7870415, Jan 11, 2011

Filed:

Aug 24, 2007

Appl. No.:

11/895589

Inventors:

Ravi Kishore Kummaraguntla - High Point NC, US
Michael Elliott - Summerfield NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 1/04

US Classification:

713503, 341118, 341126

Abstract:

Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e. g. , temperature and clock rate), the shared use reduces processor costs.

US Patent:

7889004, Feb 15, 2011

Filed:

Sep 30, 2009

Appl. No.:

12/571038

Inventors:

Scott Gregory Bardsley - Gibsonville NC, US
Michael Elliott - Summerfield NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 3/45

US Classification:

330253, 330310

Abstract:

Operational amplifier embodiments are provided to enhance amplifier parameters such as bandwidth, stability, and headroom. In an amplifier embodiment, transistor followers are arranged with first and second differential pairs to facilitate selective positioning of first and second transfer function poles to enhance bandwidth and resistors and inductors are arranged to facilitate selective positioning of complex third transfer function poles to enhance phase margin. In another amplifier embodiment, the transistor followers are arranged to reduce headroom limitations to thereby enhance the voltage swing of output signals.

US Patent:

62463535, Jun 12, 2001

Filed:

Sep 13, 1999

Appl. No.:

9/394632

Inventors:

Michael R. Elliott - Greensboro NC
Frank Murden - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 112

US Classification:

341156

Abstract:

Integrated-circuit structures and methods are provided for generating an error signal that represents temperature and process-induced signal changes in transistor parameters. In particular, a reference transistor and a sense transistor are biased to each generate a substantially temperature-insensitive minority-carrier current. The reference transistor is provided with a substantially constant voltage across its current terminals to convert its minority-carrier current into a substantially temperature-insensitive reference current I. sub. R. In contrast, the sense transistor is provided with a temperature-varying voltage across its current terminals to convert its minority-carrier current into a temperature-varying sense current I. sub. S. The reference current and the sense current are then differenced to realize an error signal I. sub. E that contains information that describes temperature and process-induced signal errors in integrated-circuit transistor stages.

US Patent:

61726362, Jan 9, 2001

Filed:

Jul 13, 1999

Appl. No.:

9/352828

Inventors:

Frank Murden - Greensboro NC
Michael R. Elliott - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 112
G06G 712

US Classification:

341155

Abstract:

Structures and methods are provided that linearize and stabilize the gain of adjustable-gain folding amplifiers. Accordingly, these folding amplifiers are suited for use in various compound ADCs where they improve the performance of subsequent folding amplifier stages, increase the number of allowed subsequent stages and replace the functions of other portions of compound ADCs (e. g. , subranging ADCs).

US Patent:

58618317, Jan 19, 1999

Filed:

Dec 23, 1996

Appl. No.:

8/772358

Inventors:

Franklin M. Murden - Greensboro NC
Carl W. Moreland - Greensboro NC
Harvey J. Ray - Salem NC
Michael R. Elliott - Greensboro NC
Marvin J. Young - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 162

US Classification:

341139

Abstract:

A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.