Michael Andrew Elliott

US Patent:

6587065, Jul 1, 2003

Filed:

Apr 29, 2002

Appl. No.:

10/136895

Inventors:

Joseph Michael Hensley - Kernersville NC
Michael R. Elliott - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 114

US Classification:

341161, 341155

Abstract:

Current-control reference systems are provided in which stabliity is realized with sensors that shift clamp windows in response to a references current-control signal to thereby maintain feedback control in the reference under steady-state and transient operating conditions.

US Patent:

7405625, Jul 29, 2008

Filed:

Apr 25, 2007

Appl. No.:

11/789858

Inventors:

Joseph Michael Hensley - Lexington NC, US
Michael R. Elliott - Summerfield NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 3/45

US Classification:

330285, 330252, 330254, 330260, 341155, 341161

Abstract:

Control structures are provided to accurately maintain amplifier common-mode levels at the predetermined level of a common-mode reference voltage V. The disclosed control structures provide amplifier feedback along a first feedback path that is configured to provide high gain and low bandwidth to closely maintain amplifier common-mode level at the predetermined level of a common-mode reference voltage V. They also provide amplifier feedback along a second feedback path that is configured to provide wide bandwidth to substantially reduce perturbations of the common-mode level that would have otherwise been induced by input signal transients. In an important amplifier feature, these controls are obtained without use of structures (e. g. , capacitors and switching transistors) that use substantial current which reduces amplifier efficiency. Although the disclosed control structures may be used in a variety of systems, they are particularly suited for use in samplers and converter stages of pipelined analog-to-digital converters.

US Patent:

7870415, Jan 11, 2011

Filed:

Aug 24, 2007

Appl. No.:

11/895589

Inventors:

Ravi Kishore Kummaraguntla - High Point NC, US
Michael Elliott - Summerfield NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 1/04

US Classification:

713503, 341118, 341126

Abstract:

Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e. g. , temperature and clock rate), the shared use reduces processor costs.

US Patent:

61632902, Dec 19, 2000

Filed:

Jul 13, 1999

Appl. No.:

9/352829

Inventors:

Carl W. Moreland - Oak Ridge NC
Michael R. Elliott - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 112

US Classification:

341155

Abstract:

Linearized unity-gain folding amplifiers include first and second differential pairs of transistors that have offset voltages between control terminals and first current terminals. The control terminals are differentially coupled through input paths to a differential input port and the joined first current terminals receive respective first and second currents through respective first and second level-shift resistors. Thus, folded and level-shifted signals can be differentially coupled via output paths between the first and second level-shift resistors and an output port. For each of the differential pairs, at least one correction voltage is generated to substantially match the offset voltage of one of the transistors of that differential pair when a differential input voltage has one polarity and the offset voltage of another of the transistors when the differential input voltage has a different polarity. The correction voltage is inserted in one of the input paths in a feedback mode of the invention and in one of the output paths in a feed-forward mode and the correction voltage is oriented to correct variations in the offset voltages of one of the differential pairs that occur adjacent a polarity transition of the differential input voltage. In serial arrangements of these amplifiers, their high linearity enhances the quantization processes of successive stages so that longer serial arrangements can be reliably used.

US Patent:

61916196, Feb 20, 2001

Filed:

Aug 24, 1999

Appl. No.:

9/382046

Inventors:

Carl W. Moreland - Oak Ridge NC
Michael R. Elliott - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 19086

US Classification:

326126

Abstract:

High-speed signal translators are provided to convert differential input signals (e. g. , ECL signals) to single-ended output signals (e. g. , CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced.