Michael Joseph Fitzpatrick

US Patent:

20090059675, Mar 5, 2009

Filed:

Aug 28, 2007

Appl. No.:

11/892874

Inventors:

Joseph T. Smith - Columbia MD, US
Dennis A. Adams - Gambrills MD, US
Stephen J. Wrazien - Cranberry PA, US
Michael D. Fitzpatrick - Baltimore MD, US
Philip Smith - Ellicott City MD, US

International Classification:

G11C 11/34
H01L 21/336
H01L 29/94

US Classification:

36518525, 257324, 438287, 257E29309, 257E21423

Abstract:

In one aspect, a radiation hardened transistor includes a buried source, buried drain and a poly-silicon gate separated from the buried source and the buried drain by a buried oxide. A recessed P+ implant or a blanket P+ implant is disposed in a substrate. A portion of the recessed P+ implant or a portion of the blanket P+ implant is disposed beneath outer edges of the poly-silicon gate, in a channel separating the buried source and the buried drain.

US Patent:

41091639, Aug 22, 1978

Filed:

Mar 11, 1977

Appl. No.:

5/776805

Inventors:

James R. Cricchi - Catonsville MD
Michael D. Fitzpatrick - Linthicum MD

Assignee:

Westinghouse Electric Corp. - Pittsburgh PA

International Classification:

H03K 502
H03K 1908
G11C 800
H03K 1934

US Classification:

307205

Abstract:

A complementary MOS voltage level shift circuit which can be used as a memory buffer circuit, for example, is disclosed. The circuit utilizes both N-channel depletion mode devices and P-channel enhancement mode MOS devices preferably fabricated on silicon-on-sapphire. Both types of devices are operated with only negative or zero gate-source voltage in order to minimize threshold voltage shifts in radiation environments. A capacitive voltage level shifting technique is used to obtain push-pull operation with driver type devices in order to reduce power consumption and increase switching speed while feeding into a capacitive load. Load type devices are used to prevent discharge of a capacitive load.

US Patent:

45758239, Mar 11, 1986

Filed:

Aug 17, 1982

Appl. No.:

6/409002

Inventors:

Michael D. Fitzpatrick - Linthicum MD

Assignee:

Westinghouse Electric Corp. - Pittsburgh PA

International Classification:

G11C 700
G11C 1140

US Classification:

365184

Abstract:

A non-volatile memory and method is described incorporating an array of variable threshold transistors, a row decoder, a buffer circuit positioned between the array and row decode circuitry, column decode circuitry, and a sense amplifier. The non-volatile memory overcomes the problem of high voltages in the memory array during READ operation. During READ operation the variable threshold transistors operate in the common source mode. A buffer circuit with level shift capability is described incorporating P and N channel transistors. A sense amplifier with decoupling during sensing or lock out is described incorporating P and N channel transistors.

US Patent:

41480490, Apr 3, 1979

Filed:

Feb 4, 1977

Appl. No.:

/765484

Inventors:

James R. Cricchi - Catonsville MD
Franklyn C. Blaha - Glen Burnie MD
Michael D. Fitzpatrick - Glen Burnie MD

Assignee:

Westinghouse Electric Corp. - Pittsburgh PA

International Classification:

H01L 2978

US Classification:

357 23

Abstract:

A radiation hardened drain-source protected MNOS transistor is disclosed. A layer of silicon oxide overlies the channel and the junctions formed by the intersections of the drain and source regions with the channel. Drain and source protection is provided by relatively thick portions of the silicon oxide layer which overlie the junctions formed by the drain and source regions and the channel. The portion of the silicon oxide layer overlying the central section of the channel is thinner than the remainder of this layer. A silicon nitride layer and an electrically conductive layer forming the gate electrode overlie the thinner portion of the silicon oxide layer to complete the MNOS transistor. The conductive layer forming gate electrode of the transistor is in electrical contact with both the silicon nitride and the silicon oxide layers. This provides a convenient method for electrons generated at the interface of the silicon and the silicon-oxide layer during irradiation to be transported to the gate, thereby preventing charge build-up in the silicon oxide which causes shifts in the characteristics of the transistor.

US Patent:

40644057, Dec 20, 1977

Filed:

Nov 9, 1976

Appl. No.:

5/740267

Inventors:

James R. Cricchi - Catonsville MD
Michael D. Fitzpatrick - Glen Burnie MD

Assignee:

Westinghouse Electric Corporation - Pittsburgh PA

International Classification:

H03K 1908
H03K 1940

US Classification:

307205

Abstract:

A complementary MOS logic circuit is disclosed. The circuit utilizes two stages with a coupling network comprising a capacitor and a diode used to couple the first stage to the second stage. This results in a circuit with the logic signal coupled to the input being inverted at the output without introducing substantial loss in signal amplitude.

US Patent:

40539164, Oct 11, 1977

Filed:

Sep 4, 1975

Appl. No.:

5/610493

Inventors:

James R. Cricchi - Catonsville MD
Michael D. Fitzpatrick - Glen Burnie MD

Assignee:

Westinghouse Electric Corporation - Pittsburgh PA

International Classification:

H01L 2712
H01L 2978
H01L 2934

US Classification:

357 23

Abstract:

An MOS transistor constructed using silicon on sapphire technology in which the channel region can be electrically connected either to the source or drain terminal is disclosed. The transistor is advantageous in that the shift of the threshold voltage of the transistor in the presence of radiation is substantially decreased. Connecting the channel region of the transistor to the source terminal also substantially reduces what is normally referred to as the "kink" effect in MOS transistors utilizing floating substrate channel regions. Reducing the sensitivity to radiation and the kink effect results in a transistor having improved electrical characteristics.

US Patent:

20200026786, Jan 23, 2020

Filed:

Jul 18, 2018

Appl. No.:

16/038682

Inventors:

- Armonk NY, US
David B. Petersen - Great Falls VA, US
Serge Bourbonnais - Palo Alto CA, US
Michael G. Fitzpatrick - Raleigh NC, US
Pamela L. McLean - Raleigh NC, US
John G. Thompson - Tucson AZ, US
Gregory W. Vance - Morgan Hill CA, US
David A. Clitherow - Bracknell, GB

International Classification:

G06F 17/30

Abstract:

A method for resynchronizing at least one batch job is provided. The method may include detecting a type of region switch request. The method may further include stopping execution workloads on a primary system based on the switch request. The method may further include suspending software and hardware data replication from the primary system to the secondary system. The method may further utilizing proxy replication engine to determine a point-in-time (PIT) at which the execution is stopped and the suspension. The method may also include switching the replication of the software and hardware data to occur the secondary system to the primary system. The method may further include synchronizing the software and hardware data up to the determined point-in-time (PIT). The method may also include activating the execution of the plurality of workloads on the secondary system based on the determined point-in-time (PIT), switching, and synchronizing.