Michael C Fitzpatrick

US Patent:

8431740, Apr 30, 2013

Filed:

Jul 21, 2010

Appl. No.:

12/804424

Inventors:

Noel Hallinan - Loveland OH, US
Michael E. Fitzpatrick - League City TX, US
John D. Hearn - Beach City TX, US
Miraj S. Patel - Sugar Land TX, US

Assignee:

Equistar Chemicals, LP - Houston TX

International Classification:

C07C 51/12

US Classification:

562519

Abstract:

Disclosed is a method for controlling the decanter phase separation of an acetic acid production by methanol carbonylation. The method comprises measuring the methyl acetate concentration of the reactor mixture, calculating the density of the decanter heavy, organic phase according to the measured methyl acetate concentration, and adjusting the conditions in the reactor or in the decanter to ensure phase separation of the decanter.

US Patent:

20130345474, Dec 26, 2013

Filed:

Jun 25, 2012

Appl. No.:

13/531987

Inventors:

Noel C. Hallinan - Loveland OH, US
Brian A. Salisbury - Oxford PA, US
Wayne J. Brtko - Cincinnati OH, US
Michael E. Fitzpatrick - League City TX, US

Assignee:

LYONDELL CHEMICAL TECHNOLOGY L.P. - Houston TX

International Classification:

C07C 51/50
C07C 53/08

US Classification:

562608, 562607

Abstract:

A process for producing acetic acid includes: obtaining hydrogen iodide in an acetic acid production system; and continually introducing a complexing agent into the system, wherein the complexing agent and hydrogen iodide interact to form a complex.

US Patent:

41091639, Aug 22, 1978

Filed:

Mar 11, 1977

Appl. No.:

5/776805

Inventors:

James R. Cricchi - Catonsville MD
Michael D. Fitzpatrick - Linthicum MD

Assignee:

Westinghouse Electric Corp. - Pittsburgh PA

International Classification:

H03K 502
H03K 1908
G11C 800
H03K 1934

US Classification:

307205

Abstract:

A complementary MOS voltage level shift circuit which can be used as a memory buffer circuit, for example, is disclosed. The circuit utilizes both N-channel depletion mode devices and P-channel enhancement mode MOS devices preferably fabricated on silicon-on-sapphire. Both types of devices are operated with only negative or zero gate-source voltage in order to minimize threshold voltage shifts in radiation environments. A capacitive voltage level shifting technique is used to obtain push-pull operation with driver type devices in order to reduce power consumption and increase switching speed while feeding into a capacitive load. Load type devices are used to prevent discharge of a capacitive load.

US Patent:

D3962989, Jul 21, 1998

Filed:

Apr 23, 1996

Appl. No.:

D/053519

Inventors:

Edward Allen Bacome - Dublin OH
Philip Glenn Fankhauser - Dublin OH
Michael Joseph Fitzpatrick - Hilliard OH

Assignee:

Epmark, Inc. - Dublin OH

International Classification:

2503

US Classification:

D25 17

US Patent:

45758239, Mar 11, 1986

Filed:

Aug 17, 1982

Appl. No.:

6/409002

Inventors:

Michael D. Fitzpatrick - Linthicum MD

Assignee:

Westinghouse Electric Corp. - Pittsburgh PA

International Classification:

G11C 700
G11C 1140

US Classification:

365184

Abstract:

A non-volatile memory and method is described incorporating an array of variable threshold transistors, a row decoder, a buffer circuit positioned between the array and row decode circuitry, column decode circuitry, and a sense amplifier. The non-volatile memory overcomes the problem of high voltages in the memory array during READ operation. During READ operation the variable threshold transistors operate in the common source mode. A buffer circuit with level shift capability is described incorporating P and N channel transistors. A sense amplifier with decoupling during sensing or lock out is described incorporating P and N channel transistors.

US Patent:

D3361373, Jun 1, 1993

Filed:

Feb 28, 1991

Appl. No.:

7/661650

Inventors:

Edward A. Bacome - Dublin OH
Philip G. Fankhauser - Dublin OH
Michael J. Fitzpatrick - Columbus OH

Assignee:

The Epcon Group, Inc. - Dublin OH

US Classification:

D25 17

US Patent:

41480490, Apr 3, 1979

Filed:

Feb 4, 1977

Appl. No.:

/765484

Inventors:

James R. Cricchi - Catonsville MD
Franklyn C. Blaha - Glen Burnie MD
Michael D. Fitzpatrick - Glen Burnie MD

Assignee:

Westinghouse Electric Corp. - Pittsburgh PA

International Classification:

H01L 2978

US Classification:

357 23

Abstract:

A radiation hardened drain-source protected MNOS transistor is disclosed. A layer of silicon oxide overlies the channel and the junctions formed by the intersections of the drain and source regions with the channel. Drain and source protection is provided by relatively thick portions of the silicon oxide layer which overlie the junctions formed by the drain and source regions and the channel. The portion of the silicon oxide layer overlying the central section of the channel is thinner than the remainder of this layer. A silicon nitride layer and an electrically conductive layer forming the gate electrode overlie the thinner portion of the silicon oxide layer to complete the MNOS transistor. The conductive layer forming gate electrode of the transistor is in electrical contact with both the silicon nitride and the silicon oxide layers. This provides a convenient method for electrons generated at the interface of the silicon and the silicon-oxide layer during irradiation to be transported to the gate, thereby preventing charge build-up in the silicon oxide which causes shifts in the characteristics of the transistor.

US Patent:

40644057, Dec 20, 1977

Filed:

Nov 9, 1976

Appl. No.:

5/740267

Inventors:

James R. Cricchi - Catonsville MD
Michael D. Fitzpatrick - Glen Burnie MD

Assignee:

Westinghouse Electric Corporation - Pittsburgh PA

International Classification:

H03K 1908
H03K 1940

US Classification:

307205

Abstract:

A complementary MOS logic circuit is disclosed. The circuit utilizes two stages with a coupling network comprising a capacitor and a diode used to couple the first stage to the second stage. This results in a circuit with the logic signal coupled to the input being inverted at the output without introducing substantial loss in signal amplitude.