Michael E Fitzsimmons

US Patent:

7185249, Feb 27, 2007

Filed:

Apr 30, 2002

Appl. No.:

10/135877

Inventors:

Thomas Tkacik - Phoeniz AZ, US
Jonathan Lutz - Kitchener, CA
Lawrence Case - Phoenix AZ, US
Douglas Hardy - Scottsdale AZ, US
Mark Redman - Gilbert AZ, US
Gregory Schmidt - Chandler AZ, US
Michael D. Fitzsimmons - Austin TX, US
Darrell L. Carder - Dripping Springs TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/28
H03K 19/00

US Classification:

714726, 326 16

Abstract:

A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.

US Patent:

7725788, May 25, 2010

Filed:

Jan 25, 2007

Appl. No.:

11/627229

Inventors:

Thomas Tkacik - Phoenix AZ, US
Jonathan Lutz - Kitchner, CA
Lawrence Case - Fountain Hills AZ, US
Douglas Hardy - Scottsdale AZ, US
Mark Redman - Gilbert AZ, US
Gregory Schmidt - Chandler AZ, US
Steven Tugenberg - Scottsdale AZ, US
Michael D. Fitzsimmons - Austin TX, US
Darrell L. Carder - Dripping Springs TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/28

US Classification:

714726

Abstract:

A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.