Michael D Floyd

US Patent:

6711706, Mar 23, 2004

Filed:

Dec 20, 2000

Appl. No.:

09/746610

Inventors:

Steven Michael Douskey - Rochester MN
Frank David Ferraiolo - Essex Junction VT
Michael Stephen Floyd - Leander TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714724, 714 30, 714733, 714734

Abstract:

A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0s on their drive interfaces, and setting all receive interfaces on the chips to receive 0s and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0s, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking test is then repeated for any additional interfaces that require testing.

US Patent:

7657893, Feb 2, 2010

Filed:

Apr 23, 2003

Appl. No.:

10/422025

Inventors:

William Joseph Armstrong - Rochester MN, US
Michael Stephen Floyd - Austin TX, US
Ronald Nick Kalla - Round Rock TX, US
Larry Scott Leitner - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46
G06F 9/44

US Classification:

718104, 712229

Abstract:

An accounting method and multi-threaded processor include a mechanism for accounting for processor resource usage by threads within programs. Relative resource use is determined by detecting a particular cycle state of threads active within the processor. If instructions are dispatched for all threads or no threads, the processor cycle is accounted equally to all threads. Alternatively if no threads are in the particular cycle state, the accounting may be made using a prior state, or in conformity with ratios of the threads' priority levels. If only one thread is in the particular cycle state, that thread is accounted the entire processor cycle. If multiple threads are dispatching, but less than all threads are dispatching, the processor cycle is billed evenly across the dispatching threads.

US Patent:

8209698, Jun 26, 2012

Filed:

Oct 15, 2009

Appl. No.:

12/579540

Inventors:

William Joseph Armstrong - Rochester MN, US
Michael Stephen Floyd - Austin TX, US
Ronald Nick Kalla - Round Rock TX, US
Larry Scott Leitner - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46
G06F 7/38

US Classification:

718104, 712229

Abstract:

Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

US Patent:

20120216210, Aug 23, 2012

Filed:

Apr 30, 2012

Appl. No.:

13/459398

Inventors:

William Joseph Armstrong - Rochester MN, US
Michael Stephen Floyd - Austin TX, US
Ronald Nick Kalla - Round Rock TX, US
Larry Scott Leitner - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US

International Classification:

G06F 9/50

US Classification:

718104

Abstract:

Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

US Patent:

20230071427, Mar 9, 2023

Filed:

Sep 8, 2022

Appl. No.:

17/940659

Inventors:

- ARMONK NY, US
BRIAN THOMAS VANDERPOOL - BYRON MN, US
PHILLIP JOHN RESTLE - KATONAH NY, US
FRANCESCO ANTHONY CAMPISANO - ROUND ROCK TX, US
MICHAEL STEPHEN FLOYD - CEDAR PARK TX, US
IAN KRISPIN CARMICHAEL - ROUND ROCK TX, US
ERIC MARZ - WILLISTON VT, US
RICHARD L. WILLAMAN - AUSTIN TX, US
MICHAEL N. GOULET - LEANDER TX, US
GREGORY SCOTT STILL - RALEIGH NC, US
RAHUL BATRA - AUSTIN TX, US
RORY TATUM - PFLUGERVILLE TX, US
ISIDORE G. BENDRIHEM - FORT LEE NJ, US

International Classification:

G06F 1/08
G06F 1/28

Abstract:

Providing deterministic frequency and voltage enhancements for a processor is disclosed. In an embodiment, a microcontroller on a processor identifies a plurality of parameters related to a processor, the plurality of parameters including at least a current supplied to the processor; determines, in dependence upon the plurality of parameters, one or more frequency scaling indexes including determining an effective switching capacitance ratio; identifies, in dependence upon the one or more frequency scaling indexes, a predetermined frequency parameter for the processor; and transitions, based on the frequency parameter, the processor to a target clock frequency. In another embodiment, a microcontroller on a processor decreases, incrementally, a power supply voltage for a processor; determines that a voltage droop parameter exceeds a voltage droop parameter threshold; and increases, incrementally, the power supply voltage in response to determining that the voltage droop parameter exceeds a voltage droop parameter threshold.

US Patent:

20230062546, Mar 2, 2023

Filed:

Aug 28, 2021

Appl. No.:

17/460163

Inventors:

- Armonk NY, US
Gerald Mark Grabowski - Kellogg MN, US
Jeffrey A. Stuecheli - Austin TX, US
Michael Stephen Floyd - Cedar Park TX, US
Matthew A. Cooke - Cedar Park TX, US

International Classification:

G06F 1/3234
G06F 1/3206

Abstract:

A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes recording an activity level of one or more processor cores within a multicore processing device and translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes determining the one or more charge replenishment requests exceeds a power delivery capacity to the multicore processing device. The method also includes regulating the processing activity of the one or more processor cores to decrease a power consumption for the one or more processing cores.