Michael Gerrod Floyd

US Patent:

8001394, Aug 16, 2011

Filed:

Jan 31, 2008

Appl. No.:

12/023536

Inventors:

Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Michael Stephen Floyd - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/26
G06F 1/32

US Classification:

713300, 713310, 713320, 716120, 716129

Abstract:

A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.

US Patent:

8156287, Apr 10, 2012

Filed:

Jan 15, 2009

Appl. No.:

12/354219

Inventors:

Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Miles Robert Dooley - Austin TX, US
Michael Stephen Floyd - Cedar Park TX, US
David Scott Ray - Georgetown TX, US
Bruce Joseph Ronchetti - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00
G06F 1/00

US Classification:

711137, 711154, 711E12057, 713300

Abstract:

A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.

US Patent:

8261276, Sep 4, 2012

Filed:

Mar 31, 2008

Appl. No.:

12/059576

Inventors:

Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Richard James Eickemeyer - Rochester MN, US
Susan Elizabeth Eisen - Round Rock TX, US
Michael Stephen Floyd - Cedar Park TX, US
Hans Mikael Jacobson - White Plains NY, US
Jeffrey R. Summers - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46
G06F 9/00
G06F 13/28
G06F 1/32

US Classification:

718103, 718108, 712233, 711135, 713320, 713321

Abstract:

A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

US Patent:

8271765, Sep 18, 2012

Filed:

Apr 8, 2009

Appl. No.:

12/420143

Inventors:

Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Michael Stephen Floyd - Cedar Park TX, US
Dung Quoc Nguyen - Austin TX, US
Bruce Joseph Ronchetti - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/00

US Classification:

712214, 712216

Abstract:

The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.

US Patent:

8271809, Sep 18, 2012

Filed:

Apr 15, 2009

Appl. No.:

12/424161

Inventors:

Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Michael Stephen Floyd - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/26
G06F 1/28
G06F 1/32

US Classification:

713300, 713310, 713320, 713321, 713322, 713324, 713330, 713340

Abstract:

Illustrative embodiments estimate power consumption within a multi-core microprocessor chip. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.

US Patent:

8516426, Aug 20, 2013

Filed:

Aug 25, 2011

Appl. No.:

13/217429

Inventors:

Pradip Bose - Yorktown Heights NY, US
Gary D. Carpenter - Austin TX, US
Michael S. Floyd - Cedar Park TX, US
Eren Kursun - Yorktown Heights NY, US
Phillip J. Restle - Katonah NY, US
Michael R. Scheuermann - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G06F 9/455
G06F 11/22

US Classification:

716120, 716133, 716136

Abstract:

A method is provided for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.

US Patent:

8635483, Jan 21, 2014

Filed:

Apr 5, 2011

Appl. No.:

13/079842

Inventors:

Emrah Acar - Montvale NJ, US
Pradip Bose - Yorktown Heights NY, US
Bishop C. Brock - Coupland TX, US
Alper Buyuktosunoglu - White Plains NY, US
Michael S. Floyd - Cedar Park TX, US
Maria L. Pesantez - Austin TX, US
Gregory S. Still - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/00
G06F 1/26
G06F 15/00
G01R 21/00
G01R 19/00

US Classification:

713340, 713320, 702 60, 702 64, 712 28

Abstract:

A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.

US Patent:

8650413, Feb 11, 2014

Filed:

Mar 29, 2010

Appl. No.:

12/749179

Inventors:

Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Michael Stephen Floyd - Cedar Park TX, US
Maria Lorena Pesantez - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/32
G06F 1/26
G06F 9/00

US Classification:

713300, 713310, 713320, 713321, 713322, 713323, 713324, 713330, 713340

Abstract:

The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value.