Michael J Floyd

US Patent:

6393594, May 21, 2002

Filed:

Aug 11, 1999

Appl. No.:

09/372698

Inventors:

Carl J. Anderson - Austin TX
Michael Stephen Floyd - Leander TX
Larry Scott Leitner - Austin TX
Bradley McCredie - Austin TX
Kevin Franklin Reick - Austin TX
Jennifer Lane Vargus - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714738, 714739, 714724

Abstract:

A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.

US Patent:

6438722, Aug 20, 2002

Filed:

Aug 11, 1999

Appl. No.:

09/372697

Inventors:

Roger Ned Bailey - Austin TX
Michael Stephen Floyd - Leander TX
Bradley McCredie - Austin TX
Kevin Franklin Reick - Austin TX
Hugh Rodney Stigdon - Georgetown TX
Jennifer Lane Vargus - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714736, 714738

Abstract:

The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.

US Patent:

6529979, Mar 4, 2003

Filed:

Nov 8, 1999

Appl. No.:

09/436105

Inventors:

Michael Stephen Floyd - Leander TX
Larry Scott Leitner - Austin TX
Kevin Franklin Reick - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1314

US Classification:

710105, 710113

Abstract:

A method and apparatus for transferring data using an on-chip bus is presented. A data transaction consisting of an address and data packet is transmitted on an on-chip bus which is a two-wire serial bus consisting of an address line and a data line that connects a plurality of satellites in a daisy-chain fashion to a central source. Each on-chip satellite is associated with a unique identifier. In response to a determination that the transaction is accepted by the satellite, which is determined by the address in the address packet positively comparing to a unique identifier for the satellite, the address packet is modified to provide a positive acknowledgment of a receipt of the address packet back to the central source of the transaction. The address packet is modified by clearing the stop bit of the address packet, i. e. gating off or negating the stop bit.

US Patent:

6539502, Mar 25, 2003

Filed:

Nov 8, 1999

Appl. No.:

09/436109

Inventors:

Joel Roger Davidson - Austin TX
Michael Stephen Floyd - Leander TX
Judith E. K. Laurens - Bastrop TX
Alexander Erik Mericas - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1130

US Classification:

714 47, 712227

Abstract:

A method and apparatus for selecting an instruction to be monitored within a pipelined processor is presented. One or more pairs of match values stored in control registers are allocated for use in instruction sampling or instruction matching. These pairs, referred to as V and V are used together to filter instructions for sampling or for instruction matching. During the fetch or decode stage, the instruction word is compared bit by bit to the V and V pair(s). For each bit in the instruction word, the corresponding bit in V and V are used to determine if a match exists. If every bit position in the instruction word results in a match, the instruction is eligible for sampling. If any bit position does not match, the instruction is not eligible. In response to a determination that the instruction is eligible for sampling, the execution of the instruction may be monitored.

US Patent:

6543003, Apr 1, 2003

Filed:

Nov 8, 1999

Appl. No.:

09/436106

Inventors:

Michael Stephen Floyd - Leander TX
James Allan Kahle - Austin TX
Hung Qui Le - Austin TX
Larry Scott Leitner - Austin TX
Kevin Franklin Reick - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 10, 714 48, 712244, 712219

Abstract:

A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.

US Patent:

6550020, Apr 15, 2003

Filed:

Jan 10, 2000

Appl. No.:

09/483260

Inventors:

Michael Stephen Floyd - Leander TX
Kevin F. Reick - Austin TX
Timothy M. Skergan - Apex NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 10, 714 11

Abstract:

A data processing system has at least one integrated circuit containing a central processing unit (CPU) that includes at least first and second processing cores. The integrated circuit also includes input facilities that receive control input specifying which of the processing cores is to be utilized. In addition, the integrated circuit includes configuration logic that decodes the control input and, in response, selectively controls reception of input signals and transmission of output signals of one or more of the processing cores in accordance with the control input. In an illustrative embodiment, the configuration logic is partial-good logic that configures the integrated circuit to utilize the second processing core, in lieu of a defective or inactive first processing core, as a virtual first processing core.

US Patent:

6587963, Jul 1, 2003

Filed:

May 12, 2000

Appl. No.:

09/569547

Inventors:

Michael Stephen Floyd - Leander TX
Kevin F. Reick - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 305

US Classification:

714 25, 714 48

Abstract:

A method of detecting a hang in a computer system, by generating a plurality of hang strobe signals, detecting that a hang has occurred in the computer system using the hang strobe signals, and determining whether the hang occurred in the processing unit or in the memory subsystem. The intervals of the hang strobe signals may be programmably set. The first hang strobe signal (for the processing unit) preferably has an interval that is longer than the second hang strobe signal (for the memory subsystem). More than two strobe signals may be provided, e. g. , for additional access layers of the memory subsystem. Hang detection may be accomplished in part by calculating a number of hang pulses that have issued during pendency of a processor instruction, and then selectively comparing the number to one of two hang limit values respectively associated with the processing unit and the memory subsystem. This selection may be based on a signal indicating whether any requests are still pending in the memory subsystem. The hang limit values can also be programmably set.

US Patent:

6629170, Sep 30, 2003

Filed:

Nov 8, 1999

Appl. No.:

09/436110

Inventors:

Joel Roger Davidson - Austin TX
Michael Stephen Floyd - Leander TX
Paul Joseph Jordan - Austin TX
Judith E. K. Laurens - Bastrop TX
Alexander Erik Mericas - Austin TX
Kevin F. Reick - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710100, 710262, 710305, 711 31, 711130, 712218, 714 37, 714 47, 702176, 702181, 702182, 702186

Abstract:

A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.