Michael D Gadberry

US Patent:

51153696, May 19, 1992

Filed:

Jan 7, 1991

Appl. No.:

7/637719

Inventors:

Stephen P. Robb - Tempe AZ
John P. Phipps - Phoenix AZ
Michael D. Gadberry - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H02H 902
H03K 1708
G05F 163

US Classification:

361 93

Abstract:

A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is coupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

US Patent:

50050613, Apr 2, 1991

Filed:

Feb 5, 1990

Appl. No.:

7/474889

Inventors:

Stephen P. Robb - Tempe AZ
John P. Phipps - Phoenix AZ
Michael D. Gadberry - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2980
H01L 2906
H01L 2910
H01L 2702

US Classification:

357 2313

Abstract:

A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is copupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

US Patent:

50878301, Feb 11, 1992

Filed:

May 22, 1989

Appl. No.:

7/354574

Inventors:

David Cave - Tokyo, JP
Michael D. Gadberry - Tempe AZ

International Classification:

H03K 301
H03K 522

US Classification:

3072966

Abstract:

A start circuit for a bandgap reference cell using CMOS transistors including a transistor connected between the bandgap reference cell and a differential amplifier in the feedback path to create an offset voltage in the bandgap reference cell when power is first applied, which offset insures the correct operation of the bandgap reference cell, and to turn off after correct operation has been achieved.