Michael W Healy

US Patent:

6949249, Sep 27, 2005

Filed:

Apr 30, 2001

Appl. No.:

10/275994

Inventors:

Michael Sean Healy - Denville NJ, US
Dennis George Anthony Nelson - Mountain Lakes NJ, US

Assignee:

Pfizer Inc. - Morris Plains NJ

International Classification:

A61K007/00
A61K031/74
A61K033/32
A61K009/00

US Classification:

424401, 424 47, 424 7803, 424 7805, 424 7806, 424400, 424642, 514865

Abstract:

A liquid, water-repellent, substantially anhydrous, spray-pumpable skin protectant composition is disclosed. The composition is designed for spraying directly onto skin, has suitable adherence to the skin, and resists running. The composition contains one or more actives, one or more rheology modifiers, and a carrier. The rheological modifiers can be waxes and/or associative thickeners such as some forms of silica. The carrier can be mineral oil or a mineral oil replacement (e. g. , isohexadecane, cyclomethicone). Film-forming components also help the composition resist running. One indication for which the composition may be formulated is diaper rash. The active ingredient for diaper rash may be dimethicone and preferably also zinc oxide.

US Patent:

20050266035, Dec 1, 2005

Filed:

Aug 11, 2005

Appl. No.:

11/202127

Inventors:

Michael Healy - Denville NJ, US
Dennis George Nelson - Mountain Lakes NJ, US

International Classification:

A61K007/00

US Classification:

424401000

Abstract:

A liquid, water-repellent, substantially anhydrous, spray-pumpable skin protectant composition is disclosed. The composition is designed for spraying directly onto skin, has suitable adherence to the skin, and resists running. The composition contains one or more actives for whichever indication the composition has been formulated, one or more rheology modifiers, and a carrier. The rheology modifiers help give the composition rheological properties such that it can be sprayed using a spray pump dispenser (i.e., a propellant-free, non-pressurized dispenser) but still resist running after it has been applied to the skin. The rheological modifiers can be waxes and/or associative thickeners such as some forms of silica. The carrier can be mineral oil or a mineral oil replacement (e.g., isohexadecane, cyclomethicone). Film-forming components also help the composition resist running. One indication for which the composition may be formulated is diaper rash. The diaper rash composition is designed for spraying onto the skin of a baby or other human (e.g., incontinent adult) for treating diaper rash. The active ingredient for diaper rash may be dimethicone and preferably also zinc oxide.

US Patent:

20090317485, Dec 24, 2009

Filed:

Dec 16, 2008

Appl. No.:

12/336007

Inventors:

Michael Sean Healy - Denville NJ, US
Dennis George Anthony Nelson - Mountain Lakes NJ, US

International Classification:

A61K 33/00

US Classification:

424600

Abstract:

A liquid, water-repellent, substantially anhydrous, spray-pumpable skin protectant composition is disclosed. The composition is designed for spraying directly onto skin, has suitable adherence to the skin, and resists running. The composition contains one or more actives, one or more rheology modifiers, and a carrier. The rheological modifiers can be waxes and/or associative thickeners such as some forms of silica. The carrier can be mineral oil or a mineral oil replacement (e.g., isohexadecane, cyclomethicone). Film-forming components also help the composition resist running. One indication for which the composition may be formulated is diaper rash. The active ingredient for diaper rash may be dimethicone and preferably also zinc oxide.

US Patent:

20130283006, Oct 24, 2013

Filed:

Sep 4, 2012

Appl. No.:

13/602807

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan Kunjunny Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/80

US Classification:

712 12, 712E09003

Abstract:

Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

US Patent:

20130283008, Oct 24, 2013

Filed:

Apr 20, 2012

Appl. No.:

13/452078

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan Kunjunny Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/02

US Classification:

712 29, 712E09002

Abstract:

Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

US Patent:

20130283009, Oct 24, 2013

Filed:

Apr 20, 2012

Appl. No.:

13/452113

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan Kunjunny Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/02

US Classification:

712 30, 712E09002

Abstract:

Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

US Patent:

20130283010, Oct 24, 2013

Filed:

Aug 31, 2012

Appl. No.:

13/601289

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan Kunjunny Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/76

US Classification:

712 30, 712E09002

Abstract:

Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

US Patent:

20140006750, Jan 2, 2014

Filed:

Sep 4, 2012

Appl. No.:

13/602777

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan K. Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/76

US Classification:

712 30, 712E09003

Abstract:

A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.