Michael J Healy

US Patent:

20130283006, Oct 24, 2013

Filed:

Sep 4, 2012

Appl. No.:

13/602807

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan Kunjunny Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/80

US Classification:

712 12, 712E09003

Abstract:

Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

US Patent:

20130283008, Oct 24, 2013

Filed:

Apr 20, 2012

Appl. No.:

13/452078

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan Kunjunny Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/02

US Classification:

712 29, 712E09002

Abstract:

Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

US Patent:

20130283009, Oct 24, 2013

Filed:

Apr 20, 2012

Appl. No.:

13/452113

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan Kunjunny Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/02

US Classification:

712 30, 712E09002

Abstract:

Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

US Patent:

20130283010, Oct 24, 2013

Filed:

Aug 31, 2012

Appl. No.:

13/601289

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan Kunjunny Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/76

US Classification:

712 30, 712E09002

Abstract:

Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

US Patent:

20140006750, Jan 2, 2014

Filed:

Sep 4, 2012

Appl. No.:

13/602777

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan K. Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/76

US Classification:

712 30, 712E09003

Abstract:

A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

US Patent:

20140006852, Jan 2, 2014

Filed:

Jun 28, 2012

Appl. No.:

13/535676

Inventors:

Alper Buyuktosunoglu - White Plains NY, US
Philip G. Emma - Danbury CT, US
Allan M. Hartstein - Chappaqua NY, US
Michael B. Healy - White Plains NY, US
Krishnan K. Kailas - Tarrytown NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/80
G06F 11/14

US Classification:

714 10, 712 12, 714E11113

Abstract:

A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

US Patent:

46073787, Aug 19, 1986

Filed:

Oct 22, 1984

Appl. No.:

6/663513

Inventors:

Gary M. Catlin - Brick NJ
Michael P. Healy - Fairfax VA

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H04L 700

US Classification:

375116

Abstract:

A detector for detecting a valid synchronizing pattern in a data frame in which a synchronizing bit pattern is multiplexed including a first register to receive the data and the synchronization bits, a pattern detector connected to the first register for detecting the synchronizing bit pattern in the first register, a second register, a source of clock pulses coupled to both said first and second registers, the elements of the second register being set to a first binary state and a density detector coupled to the second register. The clock source changes the states of successive elements of the second register from the first binary state to a second binary state as the data and synchronization bits are moved through the first register, the second register having inserted therein a signal of the first binary state upon the simultaneous detection of the synchronizing bit pattern and the conversion of a last element of said second register from a second binary state to a first binary state, and means responsive to the density detector detecting a predetermined number of elements of said second register in said first binary state to establish synchronization.

US Patent:

20200183620, Jun 11, 2020

Filed:

Dec 5, 2018

Appl. No.:

16/210708

Inventors:

- Armonk NY, US
Seokin HONG - Chappaqua NY, US
Michael HEALY - Cortlandt Manor NY, US
Bulent ABALI - Tenafly NJ, US
Alper BUYUKTOSUNOGLU - White Plains NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 3/06

Abstract:

Various embodiments are provided for enabling data compression in a computing system by a processor. Each storage block of a storage device associated with a queue may be split. Compression of data may be activated upon data occupancy within a queue exceeding a dynamic threshold. In one aspect, only a partial amount of the data is fetched, back to back, from a divided storage block in the storage block according to the queue based upon the data occupancy within the queue exceeding the dynamic threshold. A complete amount of the data may be fetched from the divided storage block in a storage block according to the queue upon the data occupancy within the queue being less than dynamic threshold.